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[AVR] Optimize 8-bit int shift
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Authored by benshi001 on Nov 3 2020, 5:14 AM.

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benshi001 created this revision.Nov 3 2020, 5:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 3 2020, 5:14 AM
benshi001 requested review of this revision.Nov 3 2020, 5:14 AM

It is hard to use SelectionDAG instead of Pseudo instructions for this optimization.

Since for LSL7, the instr serial is

ROR Rx 
CLR Rx
ROR Rx

There is no dependancy between ROR and CLR, so DAG can not be created properly.

This patch is a supplement to https://reviews.llvm.org/D89047

Now llvm-avr generates the same asm for 8-bit shifts when ShiftAmount = 1,2,3,4,5,6, 7.

Now llvm-avr generates the same asm for 8-bit shifts as AVR-GCC does, when ShiftAmount = 1,2,3,4,5,6, 7.

benshi001 updated this revision to Diff 302743.Nov 3 2020, 10:12 PM
benshi001 updated this revision to Diff 302744.Nov 3 2020, 10:18 PM
benshi001 updated this revision to Diff 303358.Nov 6 2020, 1:03 AM
dylanmckay accepted this revision.Jan 23 2021, 1:15 AM

Nice work, approved.

This revision is now accepted and ready to land.Jan 23 2021, 1:15 AM
This revision was automatically updated to reflect the committed changes.