It is hard to use SelectionDAG instead of Pseudo instructions for this optimization.
Since for LSL7, the instr serial is
There is no dependancy between ROR and CLR, so DAG can not be created properly.
This patch is a supplement to https://reviews.llvm.org/D89047
Now llvm-avr generates the same asm for 8-bit shifts when ShiftAmount = 1,2,3,4,5,6, 7.
Now llvm-avr generates the same asm for 8-bit shifts as AVR-GCC does, when ShiftAmount = 1,2,3,4,5,6, 7.
Nice work, approved.