[NFC][AMDGPU] Minor editorial improvements to AMDGPUUsage.rst

llvm/docs/AMDGPUUsage.rst

* Each CU has a separate request queue per channel. Therefore, the vector and
   ensures a previous vector memory operation has completed before executing a
   subsequent vector memory or LDS operation and so can be used to meet the
   requirements of acquire and release.
 * The L2 cache can be kept coherent with other agents on some targets, or ranges
   of virtual addresses can be set up to bypass it to ensure system coherence.
 
 Scalar memory operations are only used to access memory that is proven to not
 change during the execution of the kernel dispatch. This includes constant
-address space and global address space for program scope const variables.
+address space and global address space for program scope ``const`` variables.
 Therefore, the kernel machine code does not have to maintain the scalar cache to
 ensure it is coherent with the vector caches. The scalar and vector caches are
 invalidated between kernel dispatches by CP since constant address space data
 may change between kernel dispatch executions. See
 :ref:`amdgpu-amdhsa-memory-spaces`.
 
 The one exception is if scalar writes are used to spill SGPR registers. In this
 case the AMDGPU backend ensures the memory location used to spill is never
store        *none*       *none*         - global   - !nontemporal
                                                            1. buffer/global/flat_store
                                                               glc=1 slc=1
 
      store        *none*       *none*         - local    1. ds_store
      **Unordered Atomic**
      ------------------------------------------------------------------------------------
      load atomic  unordered    *any*          *any*      *Same as non-atomic*.
      store atomic unordered    *any*          *any*      *Same as non-atomic*.
-     atomicrmw    unordered    *any*          *any*      *Same as monotonic
-                                                         atomic*.
+     atomicrmw    unordered    *any*          *any*      *Same as monotonic atomic*.
      **Monotonic Atomic**
      ------------------------------------------------------------------------------------
      load atomic  monotonic    - singlethread - global   1. buffer/global/ds/flat_load
                                - wavefront    - local
                                - workgroup    - generic
      load atomic  monotonic    - agent        - global   1. buffer/global/flat_load
                                - system       - generic     glc=1
      store atomic monotonic    - singlethread - global   1. buffer/global/flat_store
* Each L1 quadrant of a single SA accesses a different L2 channel. Each L1
   different SAs. It ensures a previous vector memory operation has completed
   before executing a subsequent vector memory and so can be used to meet the
   requirements of acquire, release and sequential consistency.
 * The L2 cache can be kept coherent with other agents on some targets, or ranges
   of virtual addresses can be set up to bypass it to ensure system coherence.
 
 Scalar memory operations are only used to access memory that is proven to not
 change during the execution of the kernel dispatch. This includes constant
-address space and global address space for program scope const variables.
+address space and global address space for program scope ``const`` variables.
 Therefore, the kernel machine code does not have to maintain the scalar cache to
 ensure it is coherent with the vector caches. The scalar and vector caches are
 invalidated between kernel dispatches by CP since constant address space data
 may change between kernel dispatch executions. See
 :ref:`amdgpu-amdhsa-memory-spaces`.
 
 The one exception is if scalar writes are used to spill SGPR registers. In this
 case the AMDGPU backend ensures the memory location used to spill is never
store        *none*       *none*         - global   - !nontemporal
                                                             1. buffer/global/flat_store
                                                                slc=1
 
      store        *none*       *none*         - local    1. ds_store
      **Unordered Atomic**
      ------------------------------------------------------------------------------------
      load atomic  unordered    *any*          *any*      *Same as non-atomic*.
      store atomic unordered    *any*          *any*      *Same as non-atomic*.
-     atomicrmw    unordered    *any*          *any*      *Same as monotonic
-                                                         atomic*.
+     atomicrmw    unordered    *any*          *any*      *Same as monotonic atomic*.
      **Monotonic Atomic**
      ------------------------------------------------------------------------------------
      load atomic  monotonic    - singlethread - global   1. buffer/global/flat_load
                                - wavefront    - generic
      load atomic  monotonic    - workgroup    - global   1. buffer/global/flat_load
                                               - generic     glc=1
 
                                                            - If CU wavefront execution