[VE] Add +vpu attribute

[simoll]

Summary

+vpu controls whether VEISelLowering adds any vregs.
This defaults to -vpu to have scalar code generation out of the box.
We bring up vector isel under the +vpu flag. Once vector isel is stable we switch to +vpu and advertise vregs and vops in TTI.

[kaz7]

llvm/lib/Target/VE/VETargetTransformInfo.h

43

Modifications after this line look like duplicated from https://reviews.llvm.org/D90462. Otherwise, LGTM.

[simoll]

llvm/lib/Target/VE/VETargetTransformInfo.h

43

This patch depends on D90462 - you see both diffs in this Diff.
Can we commit D90462 and then rebase this patch onto upstream?

[kaz7]

llvm/lib/Target/VE/VETargetTransformInfo.h

43

I see. I was wondering why.. Now I understand it. Thanks!

[simoll]

• Removed unrelated changes.
• Added feature test.

[kaz7]

LGTM. Thank you for removing unrelated changes.

llvm/lib/Target/VE/VE.td

 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
 include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // VE Subtarget features.
 //
+def FeatureEnableVPU
+  : SubtargetFeature<"vpu", "EnableVPU", "true",
+                     "Enable the VPU">;
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "VERegisterInfo.td"
 include "VECallingConv.td"
 include "VEInstrInfo.td"

llvm/lib/Target/VE/VEISelLowering.h

 };
 }
 
 class VETargetLowering : public TargetLowering {
   const VESubtarget *Subtarget;
 
   void initRegisterClasses();
   void initSPUActions();
-  // TODO void initVPUActions();
+  void initVPUActions();
 
 public:
   VETargetLowering(const TargetMachine &TM, const VESubtarget &STI);
 
   const char *getTargetNodeName(unsigned Opcode) const override;
   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
     return MVT::i32;
   }

llvm/lib/Target/VE/VEISelLowering.cpp

 void VETargetLowering::initRegisterClasses() {
   // Set up the register classes.
   addRegisterClass(MVT::i32, &VE::I32RegClass);
   addRegisterClass(MVT::i64, &VE::I64RegClass);
   addRegisterClass(MVT::f32, &VE::F32RegClass);
   addRegisterClass(MVT::f64, &VE::I64RegClass);
   addRegisterClass(MVT::f128, &VE::F128RegClass);
 
+  if (Subtarget->enableVPU()) {
     addRegisterClass(MVT::v2i32, &VE::V64RegClass);
     addRegisterClass(MVT::v4i32, &VE::V64RegClass);
     addRegisterClass(MVT::v8i32, &VE::V64RegClass);
     addRegisterClass(MVT::v16i32, &VE::V64RegClass);
     addRegisterClass(MVT::v32i32, &VE::V64RegClass);
     addRegisterClass(MVT::v64i32, &VE::V64RegClass);
     addRegisterClass(MVT::v128i32, &VE::V64RegClass);
     addRegisterClass(MVT::v256i32, &VE::V64RegClass);
     addRegisterClass(MVT::v512i32, &VE::V64RegClass);
 
     addRegisterClass(MVT::v2i64, &VE::V64RegClass);
     addRegisterClass(MVT::v4i64, &VE::V64RegClass);
     addRegisterClass(MVT::v8i64, &VE::V64RegClass);
     addRegisterClass(MVT::v16i64, &VE::V64RegClass);
     addRegisterClass(MVT::v32i64, &VE::V64RegClass);
     addRegisterClass(MVT::v64i64, &VE::V64RegClass);
     addRegisterClass(MVT::v128i64, &VE::V64RegClass);
     addRegisterClass(MVT::v256i64, &VE::V64RegClass);
 
     addRegisterClass(MVT::v2f32, &VE::V64RegClass);
     addRegisterClass(MVT::v4f32, &VE::V64RegClass);
     addRegisterClass(MVT::v8f32, &VE::V64RegClass);
     addRegisterClass(MVT::v16f32, &VE::V64RegClass);
     addRegisterClass(MVT::v32f32, &VE::V64RegClass);
     addRegisterClass(MVT::v64f32, &VE::V64RegClass);
     addRegisterClass(MVT::v128f32, &VE::V64RegClass);
     addRegisterClass(MVT::v256f32, &VE::V64RegClass);
     addRegisterClass(MVT::v512f32, &VE::V64RegClass);
 
     addRegisterClass(MVT::v2f64, &VE::V64RegClass);
     addRegisterClass(MVT::v4f64, &VE::V64RegClass);
     addRegisterClass(MVT::v8f64, &VE::V64RegClass);
     addRegisterClass(MVT::v16f64, &VE::V64RegClass);
     addRegisterClass(MVT::v32f64, &VE::V64RegClass);
     addRegisterClass(MVT::v64f64, &VE::V64RegClass);
     addRegisterClass(MVT::v128f64, &VE::V64RegClass);
     addRegisterClass(MVT::v256f64, &VE::V64RegClass);
 
     addRegisterClass(MVT::v256i1, &VE::VMRegClass);
     addRegisterClass(MVT::v512i1, &VE::VM512RegClass);
   }
+}
 
 void VETargetLowering::initSPUActions() {
   const auto &TM = getTargetMachine();
   /// Load & Store {
 
   // VE doesn't have i1 sign extending load.
   for (MVT VT : MVT::integer_valuetypes()) {
     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
void VETargetLowering::initSPUActions() {
   setSupportsUnalignedAtomics(false);
 
   // Use custom inserter for ATOMIC_FENCE.
   setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
 
   /// } Atomic isntructions
 }
 
+void VETargetLowering::initVPUActions() {
+  // TODO upstream vector isel
+}
+
 SDValue
 VETargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                               bool IsVarArg,
                               const SmallVectorImpl<ISD::OutputArg> &Outs,
                               const SmallVectorImpl<SDValue> &OutVals,
                               const SDLoc &DL, SelectionDAG &DAG) const {
   // CCValAssign - represent the assignment of the return value to locations.
   SmallVector<CCValAssign, 16> RVLocs;
VETargetLowering::VETargetLowering(const TargetMachine &TM,
   // matters much whether it's ZeroOrOneBooleanContent, or
   // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
   // former.
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent);
 
   initRegisterClasses();
   initSPUActions();
-  // TODO initVPUActions();
+  initVPUActions();
 
   setStackPointerRegisterToSaveRestore(VE::SX11);
 
   // We have target-specific dag combine patterns for the following nodes:
   setTargetDAGCombine(ISD::TRUNCATE);
 
   // Set function alignment to 16 bytes
   setMinFunctionAlignment(Align(16));

llvm/lib/Target/VE/VESubtarget.h

 
 namespace llvm {
 class StringRef;
 
 class VESubtarget : public VEGenSubtargetInfo {
   Triple TargetTriple;
   virtual void anchor();
 
+  /// Features {
+
+  // Emit VPU instructions
+  bool EnableVPU;
+
+  /// } Features
+
   VEInstrInfo InstrInfo;
   VETargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   VEFrameLowering FrameLowering;
 
 public:
   VESubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
               const TargetMachine &TM);
 
   const VEInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const VEFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const VERegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
   const VETargetLowering *getTargetLowering() const override { return &TLInfo; }
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
   bool enableMachineScheduler() const override;
 
+  bool enableVPU() const { return EnableVPU; }
+
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
   VESubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   /// Given a actual stack size as determined by FrameInfo, this function
   /// returns adjusted framesize which includes space for register window
   /// spills and arguments.
   int getAdjustedFrameSize(int stackSize) const;
 
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/VESubtarget.cpp

 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "VEGenSubtargetInfo.inc"
 
 void VESubtarget::anchor() {}
 
 VESubtarget &VESubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                           StringRef FS) {
+  // Default feature settings
+  EnableVPU = false;
+
   // Determine default and user specified characteristics
   std::string CPUName = std::string(CPU);
   if (CPUName.empty())
     CPUName = "ve";
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPU, FS);
 

llvm/lib/Target/VE/VETargetTransformInfo.h

class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
   friend BaseT;
 
   const VESubtarget *ST;
   const VETargetLowering *TLI;
 
   const VESubtarget *getST() const { return ST; }
   const VETargetLowering *getTLI() const { return TLI; }
 
+  bool enableVPU() const { return getST()->enableVPU(); }
+
 public:
   explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
         TLI(ST->getTargetLowering()) {}
 
   unsigned getNumberOfRegisters(unsigned ClassID) const { return 64; }
 
   unsigned getRegisterBitWidth(bool Vector) const { return 64; }
 
   unsigned getMinVectorRegisterBitWidth() const { return 64; }
 };
 
 } // namespace llvm
 
 #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H

llvm/test/CodeGen/VE/Vector/feature_vpu.ll

+; RUN: llc -march=ve -mattr=help 2>&1 > /dev/null | FileCheck %s
+
+; CHECK: Available features for this target:
+; CHECK:   vpu    - Enable the VPU.
+