[ARM][SchedModels] Convert IsLdstsoScaledPred to MCSchedPredicate

[andreadb]

Nice patch!
The new predicate looks good.

It is interesting how IsLdstsoScaledPred was actually unused, and only IsLdstsoScaledPredX2 was the only used predicate.

As always, please wait for the final accept from @dmgreen as he definitely knows more than me if those new numbers are correct :).

Good job!
-Andrea

[dmgreen]

LGTM. Thanks

llvm/lib/Target/ARM/ARMBaseInstrInfo.h

bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
                          bool SkipDead) const override;
 
   bool isPredicable(const MachineInstr &MI) const override;
 
   // CPSR defined in instruction
   static bool isCPSRDefined(const MachineInstr &MI);
   bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
 
-  // Load, scaled register offset
-  bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
   // Load, scaled register offset, not plus LSL2
   bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
   // Minus reg for ldstso addr mode
   bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
   // Scaled register offset in address mode 2
   bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
   // Load multiple, base reg in list
   bool isLDMBaseRegInList(const MachineInstr &MI) const;

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
   assert(Opc.isImm());
   assert(Offset.isReg());
   int64_t OpcImm = Opc.getImm();
 
   bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub;
   return (isSub && Offset.getReg() != 0);
 }
 
-bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,
-                                       unsigned Op) const {
-  const MachineOperand &Opc = MI.getOperand(Op + 2);
-  unsigned OffImm = Opc.getImm();
-  return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
-}
-
 // Load, scaled register offset, not plus LSL2
 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
                                                   unsigned Op) const {
   const MachineOperand &Opc = MI.getOperand(Op + 2);
   unsigned OffImm = Opc.getImm();
 
   bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
   unsigned Amt = ARM_AM::getAM2Offset(OffImm);

llvm/lib/Target/ARM/ARMSchedule.td

 
 def IsCPSRDefined : CheckFunctionPredicateWithTII<
   "ARM_MC::isCPSRDefined",
   "ARMBaseInstrInfo::isCPSRDefined"
 >;
 
 def IsCPSRDefinedPred : MCSchedPredicate<IsCPSRDefined>;
 
+let FunctionMapper = "ARM_AM::getAM2ShiftOpc" in {
+  def CheckExtNoShift : CheckImmOperand_s<4, "ARM_AM::no_shift">;
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary classes used for ARM
 //
 def IIC_iALUx      : InstrItinClass;
 def IIC_iALUi      : InstrItinClass;
 def IIC_iALUr      : InstrItinClass;
 def IIC_iALUsi     : InstrItinClass;
 def IIC_iALUsir    : InstrItinClass;

llvm/lib/Target/ARM/ARMScheduleA57.td

 // Load, scaled register offset, not plus LSL2
 def IsLdstsoScaledNotOptimalPredX0 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 0)}]>;
 def IsLdstsoScaledNotOptimalPred :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 1)}]>;
 def IsLdstsoScaledNotOptimalPredX2 :
   SchedPredicate<[{TII->isLdstScaledRegNotPlusLsl2(*MI, 2)}]>;
 
-// Load, scaled register offset
-def IsLdstsoScaledPred :
-  SchedPredicate<[{TII->isLdstScaledReg(*MI, 1)}]>;
-def IsLdstsoScaledPredX2 :
-  SchedPredicate<[{TII->isLdstScaledReg(*MI, 2)}]>;
+def IsLdstsoScaledPredX2 : MCSchedPredicate<CheckNot<CheckExtNoShift>>;
 
 def IsLdstsoMinusRegPredX0 :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 0)}]>;
 def IsLdstsoMinusRegPred :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 1)}]>;
 def IsLdstsoMinusRegPredX2 :
   SchedPredicate<[{TII->isLdstSoMinusReg(*MI, 2)}]>;
 

llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file provides ARM specific target descriptions.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMMCTargetDesc.h"
+#include "ARMAddressingModes.h"
 #include "ARMBaseInfo.h"
 #include "ARMInstPrinter.h"
 #include "ARMMCAsmInfo.h"
 #include "TargetInfo/ARMTargetInfo.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/DebugInfo/CodeView/CodeView.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCCodeEmitter.h"

llvm/test/tools/llvm-mca/ARM/cortex-a57-memory-instructions.s

 # CHECK-NEXT:  1      1     1.00           *            str r8, [r12]
 # CHECK-NEXT:  1      1     1.00           *            str r7, [r1, #12]
 # CHECK-NEXT:  2      1     1.00           *            str r3, [r5, #40]!
 # CHECK-NEXT:  2      1     1.00           *            str r9, [sp], #4095
 # CHECK-NEXT:  2      1     1.00           *            str r1, [r7], #-128
 # CHECK-NEXT:  1      1     1.00           *            str r9, [r6, r3]
 # CHECK-NEXT:  1      1     1.00           *            str r8, [r0, -r2]
 # CHECK-NEXT:  2      1     1.00           *            str r7, [r1, r6]!
-# CHECK-NEXT:  2      1     1.00           *            str r7, [r1, r6, lsl #2]!
+# CHECK-NEXT:  2      2     1.00           *            str r7, [r1, r6, lsl #2]!
 # CHECK-NEXT:  2      1     1.00           *            str r6, [sp, -r1]!
 # CHECK-NEXT:  2      2     1.00           *            str r5, [r3], r9
 # CHECK-NEXT:  2      2     1.00           *            str r4, [r2], -r5
 # CHECK-NEXT:  1      1     1.00           *            str r3, [r4, -r2, lsl #2]
 # CHECK-NEXT:  2      2     1.00           *            str r2, [r7], r3, asr #24
 # CHECK-NEXT:  1      1     1.00           *            strb  r9, [r2]
 # CHECK-NEXT:  1      1     1.00           *            strb  r7, [r1, #3]
 # CHECK-NEXT:  2      1     1.00           *            strb  r6, [r4, #405]!

 # CHECK-NEXT: [2]   - A57UnitL
 # CHECK-NEXT: [3]   - A57UnitM
 # CHECK-NEXT: [4]   - A57UnitS
 # CHECK-NEXT: [5]   - A57UnitW
 # CHECK-NEXT: [6]   - A57UnitX
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]
-# CHECK-NEXT:  -     44.50  44.50  284.00 8.00   55.00   -      -
+# CHECK-NEXT:  -     44.00  44.00  284.00 9.00   55.00   -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1.0]  [1.1]  [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r5, [r7]
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     ldr r6, [r3, #63]
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r2, [r4, #4095]!
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r1, [r2], #30
 # CHECK-NEXT:  -     0.50   0.50   1.00    -      -      -      -     ldr r3, [r1], #-30

 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r8, [r12]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r7, [r1, #12]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r3, [r5, #40]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r9, [sp], #4095
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r1, [r7], #-128
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r9, [r6, r3]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r8, [r0, -r2]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r7, [r1, r6]!
-# CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r7, [r1, r6, lsl #2]!
+# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str r7, [r1, r6, lsl #2]!
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     str r6, [sp, -r1]!
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str r5, [r3], r9
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str r4, [r2], -r5
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     str r3, [r4, -r2, lsl #2]
 # CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     str r2, [r7], r3, asr #24
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strb  r9, [r2]
 # CHECK-NEXT:  -      -      -      -      -     1.00    -      -     strb  r7, [r1, #3]
 # CHECK-NEXT:  -     0.50   0.50    -      -     1.00    -      -     strb  r6, [r4, #405]!