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Fix build of MiBench on FreeBSD RISC-V
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Authored by arichardson on Oct 16 2020, 8:45 AM.

Details

Reviewers
dim
bsdjhb
jrtc27
Summary

It appears that unlike other architectures the RISC-V headers on FreeBSD
don't expose the required macros yet, so add another ifdef to check for
presence of FP_X_INV before using it.

Event Timeline

arichardson created this revision.Oct 16 2020, 8:45 AM
arichardson requested review of this revision.Oct 16 2020, 8:45 AM

Even if these were implemented on RISC-V they'd just be stubs anyway because there is no support for hardware FPU traps, you have to check fflags in software.

MultiSource/Benchmarks/MiBench/consumer-lame/lame.c
1207
dim accepted this revision.Oct 16 2020, 10:15 AM

LGTM.

MultiSource/Benchmarks/MiBench/consumer-lame/lame.c
1205

While here you might fix this typo?

This revision is now accepted and ready to land.Oct 16 2020, 10:15 AM

address feedback

arichardson marked 2 inline comments as done.Oct 17 2020, 4:38 AM
arichardson closed this revision.Oct 18 2020, 9:13 AM

Seems like the test-suite repository doesn't auto-close revisions.

Committed as https://github.com/llvm/llvm-test-suite/commit/271b87d2637e0b49b1f87a70be3473181c4cf3ac.