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Differential D86259

[AMDGPU] Correct DWARF register defintions
ClosedPublic

Authored by t-tye on Aug 19 2020, 6:15 PM.

Details

Reviewers
scott.linder
Commits
rGb690c1157e90: [AMDGPU] Correct DWARF register defintions
Summary
  • Rename AMDGPU SCC DWARF register to STATUS since the scalar condition code is a bit within the STATUS register.
  • Correct bit size of the VCC_64 register to 64 which is the size in wave64 mode.

Diff Detail

Event Timeline

t-tye created this revision.Aug 19 2020, 6:15 PM
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t-tye requested review of this revision.Aug 19 2020, 6:15 PM
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scott.linder accepted this revision.Aug 19 2020, 6:18 PM
This revision is now accepted and ready to land.Aug 19 2020, 6:18 PM
This revision was landed with ongoing or failed builds.Aug 19 2020, 6:19 PM
Closed by commit rGb690c1157e90: [AMDGPU] Correct DWARF register defintions (authored by t-tye). · Explain Why
This revision was automatically updated to reflect the committed changes.
t-tye added a commit: rGb690c1157e90: [AMDGPU] Correct DWARF register defintions.
Harbormaster completed remote builds in B68972: Diff 286698.Aug 19 2020, 7:13 PM

Revision Contents

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llvm/
docs/
4 lines

Diff 286699

llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,231 Lines • ▼ Show 20 Lines.. table:: AMDGPU DWARF Register Mapping
17 EXEC_MASK_64 64 Execution Mask Register when 17 EXEC_MASK_64 64 Execution Mask Register when
executing in wavefront 64 mode. executing in wavefront 64 mode.
18-31 *Reserved* *Reserved for highly accessed 18-31 *Reserved* *Reserved for highly accessed
registers using DWARF shortcut.* registers using DWARF shortcut.*
32-95 SGPR0-SGPR63 32 Scalar General Purpose 32-95 SGPR0-SGPR63 32 Scalar General Purpose
Registers. Registers.
96-127 *Reserved* *Reserved for frequently accessed 96-127 *Reserved* *Reserved for frequently accessed
registers using DWARF 1-byte ULEB.* registers using DWARF 1-byte ULEB.*
128 SCC 32 Scalar Condition Code Register. 128 STATUS 32 Status Register.
129-511 *Reserved* *Reserved for future Scalar 129-511 *Reserved* *Reserved for future Scalar
Architectural Registers.* Architectural Registers.*
512 VCC_32 32 Vector Condition Code Register 512 VCC_32 32 Vector Condition Code Register
when executing in wavefront 32 when executing in wavefront 32
mode. mode.
513-1023 *Reserved* *Reserved for future Vector 513-1023 *Reserved* *Reserved for future Vector
Architectural Registers when Architectural Registers when
executing in wavefront 32 mode.* executing in wavefront 32 mode.*
768 VCC_64 32 Vector Condition Code Register 768 VCC_64 64 Vector Condition Code Register
when executing in wavefront 64 when executing in wavefront 64
mode. mode.
769-1023 *Reserved* *Reserved for future Vector 769-1023 *Reserved* *Reserved for future Vector
Architectural Registers when Architectural Registers when
executing in wavefront 64 mode.* executing in wavefront 64 mode.*
1024-1087 *Reserved* *Reserved for padding.* 1024-1087 *Reserved* *Reserved for padding.*
1088-1129 SGPR64-SGPR105 32 Scalar General Purpose Registers. 1088-1129 SGPR64-SGPR105 32 Scalar General Purpose Registers.
1130-1535 *Reserved* *Reserved for future Scalar 1130-1535 *Reserved* *Reserved for future Scalar
▲ Show 20 Lines • Show All 6,566 Lines • Show Last 20 Lines