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Differential D86009

AMDGPU: Fix global atomic saddr operand class
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Authored by arsenm on Aug 14 2020, 5:21 PM.

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Reviewers
rampitec
kzhuravl

Diff Detail

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arsenm created this revision.Aug 14 2020, 5:21 PM
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rampitec accepted this revision.Aug 14 2020, 5:25 PM
This revision is now accepted and ready to land.Aug 14 2020, 5:25 PM
arsenm closed this revision.Aug 15 2020, 9:27 AM

a7455652c04c927bc967d7c3f7bda90620d5d546

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
12 lines
MC/
AMDGPU/
4 lines
Disassembler/
AMDGPU/
8 lines
4 lines

Diff 285796

llvm/lib/Target/AMDGPU/FLATInstructions.td

Show First 20 Lines • Show All 349 Lines • ▼ Show 20 Lines def "" : FLAT_AtomicNoRet_Pseudo <opName,
AtomicNoRet <opName, 0> { AtomicNoRet <opName, 0> {
let has_saddr = 1; let has_saddr = 1;
let PseudoInstr = NAME; let PseudoInstr = NAME;
let FPAtomic = isFP; let FPAtomic = isFP;
} }
def _SADDR : FLAT_AtomicNoRet_Pseudo <opName, def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
(outs), (outs),
(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC_0:$slc), (ins VGPR_32:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC_0:$slc),
" $vaddr, $vdata, $saddr$offset$slc">, " $vaddr, $vdata, $saddr$offset$slc">,
GlobalSaddrTable<1, opName>, GlobalSaddrTable<1, opName>,
AtomicNoRet <opName#"_saddr", 0> { AtomicNoRet <opName#"_saddr", 0> {
let has_saddr = 1; let has_saddr = 1;
let enabled_saddr = 1; let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR"; let PseudoInstr = NAME#"_SADDR";
let FPAtomic = isFP; let FPAtomic = isFP;
} }
Show All 17 Lines [(set vt:$vdst,
GlobalSaddrTable<0, opName#"_rtn">, GlobalSaddrTable<0, opName#"_rtn">,
AtomicNoRet <opName, 1> { AtomicNoRet <opName, 1> {
let has_saddr = 1; let has_saddr = 1;
let FPAtomic = isFP; let FPAtomic = isFP;
} }
def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName, def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst), (outs vdst_rc:$vdst),
(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC_0:$slc), (ins VGPR_32:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC_0:$slc),
" $vdst, $vaddr, $vdata, $saddr$offset glc$slc">, " $vdst, $vaddr, $vdata, $saddr$offset glc$slc">,
GlobalSaddrTable<1, opName#"_rtn">, GlobalSaddrTable<1, opName#"_rtn">,
AtomicNoRet <opName#"_saddr", 1> { AtomicNoRet <opName#"_saddr", 1> {
let has_saddr = 1; let has_saddr = 1;
let enabled_saddr = 1; let enabled_saddr = 1;
let PseudoInstr = NAME#"_SADDR_RTN"; let PseudoInstr = NAME#"_SADDR_RTN";
let FPAtomic = isFP; let FPAtomic = isFP;
} }
▲ Show 20 Lines • Show All 1,008 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir

Show First 20 Lines • Show All 340 Lines • ▼ Show 20 Lines
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
name: global_atomic_fcmpswap_saddr_to_s_denorm_mode name: global_atomic_fcmpswap_saddr_to_s_denorm_mode
body: | body: |
bb.0: bb.0:
GLOBAL_ATOMIC_FCMPSWAP_SADDR undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`) GLOBAL_ATOMIC_FCMPSWAP_SADDR undef %0:vgpr_32, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
S_DENORM_MODE 0, implicit-def $mode, implicit $mode S_DENORM_MODE 0, implicit-def $mode, implicit $mode
... ...
# GCN-LABEL: name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode # GCN-LABEL: name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
# GCN: GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN # GCN: GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
body: | body: |
bb.0: bb.0:
%2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`) %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN undef %0:vgpr_32, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
S_DENORM_MODE 0, implicit-def $mode, implicit $mode S_DENORM_MODE 0, implicit-def $mode, implicit $mode
... ...
# GCN-LABEL: name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode # GCN-LABEL: name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode
# GCN: GLOBAL_ATOMIC_FMAX_SADDR_RTN # GCN: GLOBAL_ATOMIC_FMAX_SADDR_RTN
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode
body: | body: |
bb.0: bb.0:
%2:vgpr_32 = GLOBAL_ATOMIC_FMAX_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`) %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_SADDR_RTN undef %0:vgpr_32, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
S_DENORM_MODE 0, implicit-def $mode, implicit $mode S_DENORM_MODE 0, implicit-def $mode, implicit $mode
... ...
# GCN-LABEL: name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode # GCN-LABEL: name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
# GCN: GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN # GCN: GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
body: | body: |
bb.0: bb.0:
%2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`) %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN undef %0:vgpr_32, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
S_DENORM_MODE 0, implicit-def $mode, implicit $mode S_DENORM_MODE 0, implicit-def $mode, implicit $mode
... ...
# GCN-LABEL: name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode # GCN-LABEL: name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode
# GCN: GLOBAL_ATOMIC_FMIN_SADDR_RTN # GCN: GLOBAL_ATOMIC_FMIN_SADDR_RTN
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode
body: | body: |
bb.0: bb.0:
%2:vgpr_32 = GLOBAL_ATOMIC_FMIN_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`) %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_SADDR_RTN undef %0:vgpr_32, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
S_DENORM_MODE 0, implicit-def $mode, implicit $mode S_DENORM_MODE 0, implicit-def $mode, implicit $mode
... ...
# GCN-LABEL: name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode # GCN-LABEL: name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
# GCN: GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN # GCN: GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0 # GCN-NEXT: S_NOP 0
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
body: | body: |
bb.0: bb.0:
%2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`) %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN undef %0:vgpr_32, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
S_DENORM_MODE 0, implicit-def $mode, implicit $mode S_DENORM_MODE 0, implicit-def $mode, implicit $mode
... ...
# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_waitcnt # GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_waitcnt
# GCN: FLAT_ATOMIC_FMIN # GCN: FLAT_ATOMIC_FMIN
# GCN-NEXT: S_WAITCNT # GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_DENORM_MODE # GCN-NEXT: S_DENORM_MODE
--- ---
Show All 20 Lines

llvm/test/MC/AMDGPU/gfx1030_new.s

Show All 13 Lines
// GFX10: encoding: [0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00] // GFX10: encoding: [0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00]
global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc
// GFX10: encoding: [0x64,0x80,0xd3,0xdc,0x00,0x02,0x7d,0x02] // GFX10: encoding: [0x64,0x80,0xd3,0xdc,0x00,0x02,0x7d,0x02]
global_atomic_csub v2, v[0:1], v2, off global_atomic_csub v2, v[0:1], v2, off
// GFX10: encoding: [0x00,0x80,0xd1,0xdc,0x00,0x02,0x7d,0x02] // GFX10: encoding: [0x00,0x80,0xd1,0xdc,0x00,0x02,0x7d,0x02]
global_atomic_csub v2, v[0:1], v2, s[2:3] global_atomic_csub v2, v0, v2, s[2:3]
// GFX10: encoding: [0x00,0x80,0xd1,0xdc,0x00,0x02,0x02,0x02] // GFX10: encoding: [0x00,0x80,0xd1,0xdc,0x00,0x02,0x02,0x02]
global_atomic_csub v2, v[0:1], v2, s[2:3] offset:100 glc slc global_atomic_csub v2, v0, v2, s[2:3] offset:100 glc slc
// GFX10: encoding: [0x64,0x80,0xd3,0xdc,0x00,0x02,0x02,0x02] // GFX10: encoding: [0x64,0x80,0xd3,0xdc,0x00,0x02,0x02,0x02]
buffer_atomic_csub v5, off, s[8:11], s3 buffer_atomic_csub v5, off, s[8:11], s3
// GFX10: encoding: [0x00,0x40,0xd0,0xe0,0x00,0x05,0x02,0x03] // GFX10: encoding: [0x00,0x40,0xd0,0xe0,0x00,0x05,0x02,0x03]
buffer_atomic_csub v5, off, s[8:11], s3 offset:4095 glc buffer_atomic_csub v5, off, s[8:11], s3 offset:4095 glc
// GFX10: encoding: [0xff,0x4f,0xd0,0xe0,0x00,0x05,0x02,0x03] // GFX10: encoding: [0xff,0x4f,0xd0,0xe0,0x00,0x05,0x02,0x03]
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/MC/Disassembler/AMDGPU/flat_gfx9.txt

Show All 36 Lines
0x00,0x00,0x60,0xdc,0x00,0x00,0x00,0x00 0x00,0x00,0x60,0xdc,0x00,0x00,0x00,0x00
# CHECK: flat_store_byte v[0:1], v0 offset:7 ; encoding: [0x07,0x00,0x60,0xdc,0x00,0x00,0x00,0x00] # CHECK: flat_store_byte v[0:1], v0 offset:7 ; encoding: [0x07,0x00,0x60,0xdc,0x00,0x00,0x00,0x00]
0x07,0x00,0x60,0xdc,0x00,0x00,0x00,0x00 0x07,0x00,0x60,0xdc,0x00,0x00,0x00,0x00
# CHECK: flat_store_byte v[0:1], v0 offset:4095 glc ; encoding: [0xff,0x0f,0x61,0xdc,0x00,0x00,0x00,0x00] # CHECK: flat_store_byte v[0:1], v0 offset:4095 glc ; encoding: [0xff,0x0f,0x61,0xdc,0x00,0x00,0x00,0x00]
0xff,0x0f,0x61,0xdc,0x00,0x00,0x00,0x00 0xff,0x0f,0x61,0xdc,0x00,0x00,0x00,0x00
# CHECK: global_atomic_add v[2:3], v4, s[0:1] ; encoding: [0x00,0x80,0x08,0xdd,0x02,0x04,0x00,0x00] # CHECK: global_atomic_add v2, v4, s[0:1] ; encoding: [0x00,0x80,0x08,0xdd,0x02,0x04,0x00,0x00]
0x00,0x80,0x08,0xdd,0x02,0x04,0x00,0x00 0x00,0x80,0x08,0xdd,0x02,0x04,0x00,0x00
# CHECK: global_atomic_add v[2:3], v4, s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x08,0xdd,0x02,0x04,0x00,0x00] # CHECK: global_atomic_add v2, v4, s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x08,0xdd,0x02,0x04,0x00,0x00]
0xff,0x8f,0x08,0xdd,0x02,0x04,0x00,0x00 0xff,0x8f,0x08,0xdd,0x02,0x04,0x00,0x00
# CHECK: global_atomic_add v[2:3], v4, s[0:1] offset:-4096 ; encoding: [0x00,0x90,0x08,0xdd,0x02,0x04,0x00,0x00] # CHECK: global_atomic_add v2, v4, s[0:1] offset:-4096 ; encoding: [0x00,0x90,0x08,0xdd,0x02,0x04,0x00,0x00]
0x00,0x90,0x08,0xdd,0x02,0x04,0x00,0x00 0x00,0x90,0x08,0xdd,0x02,0x04,0x00,0x00
# CHECK: global_atomic_add v0, v[2:3], v4, s[0:1] offset:-1 glc ; encoding: [0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00] # CHECK: global_atomic_add v0, v2, v4, s[0:1] offset:-1 glc ; encoding: [0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00]
0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00 0xff,0x9f,0x09,0xdd,0x02,0x04,0x00,0x00
# CHECK: global_load_sbyte v0, v2, s[0:1] ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00] # CHECK: global_load_sbyte v0, v2, s[0:1] ; encoding: [0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00]
0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00 0x00,0x80,0x44,0xdc,0x02,0x00,0x00,0x00
# CHECK: global_load_sbyte v0, v2, s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00] # CHECK: global_load_sbyte v0, v2, s[0:1] offset:4095 ; encoding: [0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00]
0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00 0xff,0x8f,0x44,0xdc,0x02,0x00,0x00,0x00
Show All 35 Lines

llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt

Show All 13 Lines
0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00 0x10,0x80,0x70,0xdc,0xfe,0x01,0x02,0x00
# GFX10: global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc # GFX10: global_atomic_csub v2, v[0:1], v2, off offset:100 glc slc
0x64,0x80,0xd3,0xdc,0x00,0x02,0x7d,0x02 0x64,0x80,0xd3,0xdc,0x00,0x02,0x7d,0x02
# GFX10: global_atomic_csub v2, v[0:1], v2, off glc # GFX10: global_atomic_csub v2, v[0:1], v2, off glc
0x00,0x80,0xd1,0xdc,0x00,0x02,0x7d,0x02 0x00,0x80,0xd1,0xdc,0x00,0x02,0x7d,0x02
# GFX10: global_atomic_csub v2, v[0:1], v2, s[2:3] glc # GFX10: global_atomic_csub v2, v0, v2, s[2:3] glc
0x00,0x80,0xd1,0xdc,0x00,0x02,0x02,0x02 0x00,0x80,0xd1,0xdc,0x00,0x02,0x02,0x02
# GFX10: global_atomic_csub v2, v[0:1], v2, s[2:3] offset:100 glc slc # GFX10: global_atomic_csub v2, v0, v2, s[2:3] offset:100 glc slc
0x64,0x80,0xd3,0xdc,0x00,0x02,0x02,0x02 0x64,0x80,0xd3,0xdc,0x00,0x02,0x02,0x02
# GFX10: buffer_atomic_csub v5, off, s[8:11], s3 # GFX10: buffer_atomic_csub v5, off, s[8:11], s3
0x00,0x40,0xd0,0xe0,0x00,0x05,0x02,0x03 0x00,0x40,0xd0,0xe0,0x00,0x05,0x02,0x03
# GFX10: buffer_atomic_csub v5, off, s[8:11], s3 offset:4095 glc # GFX10: buffer_atomic_csub v5, off, s[8:11], s3 offset:4095 glc
0xff,0x4f,0xd0,0xe0,0x00,0x05,0x02,0x03 0xff,0x4f,0xd0,0xe0,0x00,0x05,0x02,0x03
Show All 35 Lines