[VE] Optimize trunc related instructions

[kaz7]

Summary

Change to not generate truncate instructions if all use of a truncate
operation don't care about higher bits. For example, an i32 add
instruction doesn't care about higher 32 bits in 64 bit registers.
Updates regression tests also.

[kaz7]

Update following clang-tidy comments.

[simoll]

Nice! LGTM :)

llvm/lib/Target/VE/VEISelLowering.h

public:
   SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
   /// } Custom Lower
 
+  /// Custom DAGCombine {
+  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+
+  SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
+  /// } Custom DAGCombine
+
   SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
   SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
                        SelectionDAG &DAG) const;
   SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const;
 
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
   /// Returns true if the target allows unaligned memory accesses of the

llvm/lib/Target/VE/VEISelLowering.cpp

VETargetLowering::VETargetLowering(const TargetMachine &TM,
   for (MVT FPVT : MVT::fp_valuetypes()) {
     setOperationAction(ISD::FP16_TO_FP, FPVT, Expand);
     setOperationAction(ISD::FP_TO_FP16, FPVT, Expand);
   }
   /// } Conversion
 
   setStackPointerRegisterToSaveRestore(VE::SX11);
 
+  // We have target-specific dag combine patterns for the following nodes:
+  setTargetDAGCombine(ISD::TRUNCATE);
+
   // Set function alignment to 16 bytes
   setMinFunctionAlignment(Align(16));
 
   // VE stores all argument by 8 bytes alignment
   setMinStackArgumentAlignment(Align(8));
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 }
case ISD::GlobalTLSAddress:
     return LowerGlobalTLSAddress(Op, DAG);
   case ISD::VASTART:
     return LowerVASTART(Op, DAG);
   case ISD::VAARG:
     return LowerVAARG(Op, DAG);
   }
 }
 /// } Custom Lower
+
+static bool isI32Insn(const SDNode *User, const SDNode *N) {
+  switch (User->getOpcode()) {
+  default:
+    return false;
+  case ISD::ADD:
+  case ISD::SUB:
+  case ISD::MUL:
+  case ISD::SDIV:
+  case ISD::UDIV:
+  case ISD::SETCC:
+  case ISD::SMIN:
+  case ISD::SMAX:
+  case ISD::SHL:
+  case ISD::SRA:
+  case ISD::BSWAP:
+  case ISD::SINT_TO_FP:
+  case ISD::UINT_TO_FP:
+  case ISD::BR_CC:
+  case ISD::BITCAST:
+  case ISD::ATOMIC_CMP_SWAP:
+  case ISD::ATOMIC_SWAP:
+    return true;
+  case ISD::SRL:
+    if (N->getOperand(0).getOpcode() != ISD::SRL)
+      return true;
+    // (srl (trunc (srl ...))) may be optimized by combining srl, so
+    // doesn't optimize trunc now.
+    return false;
+  case ISD::SELECT_CC:
+    if (User->getOperand(2).getNode() != N &&
+        User->getOperand(3).getNode() != N)
+      return true;
+    LLVM_FALLTHROUGH;
+  case ISD::AND:
+  case ISD::OR:
+  case ISD::XOR:
+  case ISD::SELECT:
+  case ISD::CopyToReg:
+    // Check all use of selections, bit operations, and copies.  If all of them
+    // are safe, optimize truncate to extract_subreg.
+    for (SDNode::use_iterator UI = User->use_begin(), UE = User->use_end();
+         UI != UE; ++UI) {
+      switch ((*UI)->getOpcode()) {
+      default:
+        // If the use is an instruction which treats the source operand as i32,
+        // it is safe to avoid truncate here.
+        if (isI32Insn(*UI, N))
+          continue;
+        break;
+      case ISD::ANY_EXTEND:
+      case ISD::SIGN_EXTEND:
+      case ISD::ZERO_EXTEND: {
+        // Special optimizations to the combination of ext and trunc.
+        // (ext ... (select ... (trunc ...))) is safe to avoid truncate here
+        // since this truncate instruction clears higher 32 bits which is filled
+        // by one of ext instructions later.
+        assert(N->getValueType(0) == MVT::i32 &&
+               "find truncate to not i32 integer");
+        if (User->getOpcode() == ISD::SELECT_CC ||
+            User->getOpcode() == ISD::SELECT)
+          continue;
+        break;
+      }
+      }
+      return false;
+    }
+    return true;
+  }
+}
+
+// Optimize TRUNCATE in DAG combining.  Optimizing it in CUSTOM lower is
+// sometime too early.  Optimizing it in DAG pattern matching in VEInstrInfo.td
+// is sometime too late.  So, doing it at here.
+SDValue VETargetLowering::combineTRUNCATE(SDNode *N,
+                                          DAGCombinerInfo &DCI) const {
+  assert(N->getOpcode() == ISD::TRUNCATE &&
+         "Should be called with a TRUNCATE node");
+
+  SelectionDAG &DAG = DCI.DAG;
+  SDLoc DL(N);
+  EVT VT = N->getValueType(0);
+
+  // We prefer to do this when all types are legal.
+  if (!DCI.isAfterLegalizeDAG())
+    return SDValue();
+
+  // Skip combine TRUNCATE atm if the operand of TRUNCATE might be a constant.
+  if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC &&
+      isa<ConstantSDNode>(N->getOperand(0)->getOperand(0)) &&
+      isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
+    return SDValue();
+
+  // Check all use of this TRUNCATE.
+  for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE;
+       ++UI) {
+    SDNode *User = *UI;
+
+    // Make sure that we're not going to replace TRUNCATE for non i32
+    // instructions.
+    //
+    // FIXME: Although we could sometimes handle this, and it does occur in
+    // practice that one of the condition inputs to the select is also one of
+    // the outputs, we currently can't deal with this.
+    if (isI32Insn(User, N))
+      continue;
+
+    return SDValue();
+  }
+
+  SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32);
+  return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, VT,
+                                    N->getOperand(0), SubI32),
+                 0);
+}
+
+SDValue VETargetLowering::PerformDAGCombine(SDNode *N,
+                                            DAGCombinerInfo &DCI) const {
+  switch (N->getOpcode()) {
+  default:
+    break;
+  case ISD::TRUNCATE:
+    return combineTRUNCATE(N, DCI);
+  }
+
+  return SDValue();
+}

llvm/test/CodeGen/VE/addition.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %0, i8 signext %1) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i8 %1, %0
   ret i8 %3
 }
 
 define signext i16 @func2(i16 signext %0, i16 signext %1) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i16 %1, %0
   ret i16 %3
 }
 
 define i32 @func3(i32 %0, i32 %1) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add nsw i32 %1, %0
   ret i32 %3
 }
 
 define i64 @func4(i64 %0, i64 %1) {
 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add nsw i64 %1, %0
   ret i64 %3
 }
 
 define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i8 %1, %0
   ret i8 %3
 }
 
 define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i16 %1, %0
   ret i16 %3
 }
 
 define i32 @func8(i32 %0, i32 %1) {
 ; CHECK-LABEL: func8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i32 %1, %0
   ret i32 %3
 }
 
 define i64 @func9(i64 %0, i64 %1) {
 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    adds.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i64 %1, %0
   ret i64 %3
 }
 
 define signext i8 @func13(i8 signext %0) {
 ; CHECK-LABEL: func13:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add i8 %0, 5
   ret i8 %2
 }
 
 define signext i16 @func14(i16 signext %0) {
 ; CHECK-LABEL: func14:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add i16 %0, 5
   ret i16 %2
 }
 
 define i32 @func15(i32 %0) {
 ; CHECK-LABEL: func15:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add nsw i32 %0, 5
   ret i32 %2
 }
 
 define i64 @func16(i64 %0) {
 ; CHECK-LABEL: func16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, 5(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add nsw i64 %0, 5
   ret i64 %2
 }
 
 define zeroext i8 @func18(i8 zeroext %0) {
 ; CHECK-LABEL: func18:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add i8 %0, 5
   ret i8 %2
 }
 
 define zeroext i16 @func19(i16 zeroext %0) {
 ; CHECK-LABEL: func19:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add i16 %0, 5
   ret i16 %2
 }
 
 define i32 @func20(i32 %0) {
 ; CHECK-LABEL: func20:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = add i32 %0, 5
   ret i32 %2
 }
 
 define i64 @func21(i64 %0) {
 ; CHECK-LABEL: func21:

llvm/test/CodeGen/VE/bitcast.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %r = bitcast i64 %x to double
   ret double %r
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local float @bitcastw2f(i32 %x) {
 ; CHECK-LABEL: bitcastw2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, 32
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = bitcast i32 %x to float
   ret float %r
 }
 
 ; Function Attrs: noinline nounwind optnone
 define dso_local i32 @bitcastf2w(float %x) {
 ; CHECK-LABEL: bitcastf2w:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sra.l %s0, %s0, 32
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = bitcast float %x to i32
   ret i32 %r
 }

llvm/test/CodeGen/VE/branch1.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    brle.w %s0, %s1, .LBB{{[0-9]+}}_1
 ; CHECK-NEXT:  # %bb.2: # %on.true
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
join:
   ret i8 %r
 }
 
 declare i32 @ret(i32)
 
 define i32 @func2(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    brle.w %s0, %s1, .LBB{{[0-9]+}}_1
 ; CHECK-NEXT:  # %bb.2: # %on.true
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1

 join:
   %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
   ret i32 %r
 }
 
 define i32 @func3(i32 %a, i32 %b) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    brle.w %s0, %s1, .LBB{{[0-9]+}}_1
 ; CHECK-NEXT:  # %bb.2: # %on.true
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1

 join:
   %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
   ret i32 %r
 }
 
 define i32 @func5(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: func5:
 ; CHECK:       .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
 ; CHECK-NEXT:    brle.w 0, %s0, .LBB{{[0-9]+}}_1
 ; CHECK-NEXT:  # %bb.2: # %on.true
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)

 join:
   %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
   ret i32 %r
 }
 
 define i32 @func6(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
 ; CHECK-NEXT:    brle.w 0, %s0, .LBB{{[0-9]+}}_1
 ; CHECK-NEXT:  # %bb.2: # %on.true
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)

 join:
   %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
   ret i32 %r
 }
 
 define i32 @func7(i32 %a, i32 %b) {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_5:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
 ; CHECK-NEXT:    brle.w 0, %s0, .LBB{{[0-9]+}}_1
 ; CHECK-NEXT:  # %bb.2: # %on.true
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
 ; CHECK-NEXT:    bsic %s10, (, %s12)

llvm/test/CodeGen/VE/bswap.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i64 @func1(i64 %p) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    bswp %s0, %s0, 0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i64 @llvm.bswap.i64(i64 %p)
   ret i64 %r
 }
 
 declare i64 @llvm.bswap.i64(i64)
 
 define i32 @func2(i32 %p) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    bswp %s0, %s0, 1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @llvm.bswap.i32(i32 %p)
   ret i32 %r
 }
 
 declare i32 @llvm.bswap.i32(i32)
 
 define signext i16 @func3(i16 signext %p) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    bswp %s0, %s0, 1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, 16
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i16 @llvm.bswap.i16(i16 %p)
   ret i16 %r
 }
 
 declare i16 @llvm.bswap.i16(i16)
 
 define i64 @func4(i64 %p) {
 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    bswp %s0, %s0, 0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i64 @llvm.bswap.i64(i64 %p)
   ret i64 %r
 }
 
 define i32 @func5(i32 %p) {
 ; CHECK-LABEL: func5:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    bswp %s0, %s0, 1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @llvm.bswap.i32(i32 %p)
   ret i32 %r
 }
 
 define zeroext i16 @func6(i16 zeroext %p) {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    bswp %s0, %s0, 1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, 16
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i16 @llvm.bswap.i16(i16 %p)
   ret i16 %r
 }

llvm/test/CodeGen/VE/cast.ll

 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = sext i32 %0 to i64
   ret i64 %2
 }
 
 define float @i2f(i32 %x) {
 ; CHECK-LABEL: i2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sitofp i32 %x to float
   ret float %r
 }
 
 define double @i2d(i32 %x) {
 ; CHECK-LABEL: i2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sitofp i32 %x to double
   ret double %r
 }
 
 define signext i8 @ui2c(i32 %0) {
 ; CHECK-LABEL: ui2c:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = sext i16 %0 to i64
   ret i64 %2
 }
 
 define float @s2f(i16 signext %x) {
 ; CHECK-LABEL: s2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sitofp i16 %x to float
   ret float %r
 }
 
 define double @s2d(i16 signext %x) {
 ; CHECK-LABEL: s2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sitofp i16 %x to double
   ret double %r
 }
 
 define signext i8 @us2c(i16 zeroext %0) {
 ; CHECK-LABEL: us2c:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = zext i16 %0 to i64
   ret i64 %2
 }
 
 define float @us2f(i16 zeroext %x) {
 ; CHECK-LABEL: us2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = uitofp i16 %x to float
   ret float %r
 }
 
 define double @us2d(i16 zeroext %x) {
 ; CHECK-LABEL: us2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = uitofp i16 %x to double
   ret double %r
 }
 
 define signext i8 @c2c(i8 returned signext %0) {
 ; CHECK-LABEL: c2c:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = sext i8 %0 to i64
   ret i64 %2
 }
 
 define float @c2f(i8 signext %x) {
 ; CHECK-LABEL: c2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sitofp i8 %x to float
   ret float %r
 }
 
 define double @c2d(i8 signext %x) {
 ; CHECK-LABEL: c2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sitofp i8 %x to double
   ret double %r
 }
 
 define signext i8 @uc2c(i8 returned zeroext %0) {
 ; CHECK-LABEL: uc2c:

 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = zext i8 %0 to i64
   ret i64 %2
 }
 
 define float @uc2f(i8 zeroext %x) {
 ; CHECK-LABEL: uc2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = uitofp i8 %x to float
   ret float %r
 }
 
 define double @uc2d(i8 zeroext %x) {
 ; CHECK-LABEL: uc2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = uitofp i8 %x to double
   ret double %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i128 @i128() {

llvm/test/CodeGen/VE/div.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divi64(i64 %a, i64 %b) {
 ; CHECK-LABEL: divi64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i64 %a, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @divi32(i32 %a, i32 %b) {
 ; CHECK-LABEL: divi32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i32 %a, %b
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divu64(i64 %a, i64 %b) {
 ; CHECK-LABEL: divu64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i64 %a, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @divu32(i32 %a, i32 %b) {
 ; CHECK-LABEL: divu32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i32 %a, %b
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @divi16(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: divi16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a32 = sext i16 %a to i32
   %b32 = sext i16 %b to i32
   %r32 = sdiv i32 %a32, %b32
   %r = trunc i32 %r32 to i16
   ret i16 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @divu16(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: divu16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i16 %a, %b
   ret i16 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @divi8(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: divi8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a32 = sext i8 %a to i32
   %b32 = sext i8 %b to i32
   %r32 = sdiv i32 %a32, %b32
   %r = trunc i32 %r32 to i8
   ret i8 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @divu8(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: divu8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i8 %a, %b
   ret i8 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divi64ri(i64 %a, i64 %b) {
 ; CHECK-LABEL: divi64ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.l %s0, %s0, (62)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i64 %a, 3
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @divi32ri(i32 %a, i32 %b) {
 ; CHECK-LABEL: divi32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s0, %s0, (62)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i32 %a, 3
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divu64ri(i64 %a, i64 %b) {
 ; CHECK-LABEL: divu64ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s0, %s0, (62)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i64 %a, 3
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @divu32ri(i32 %a, i32 %b) {
 ; CHECK-LABEL: divu32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s0, %s0, (62)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i32 %a, 3
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divi64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: divi64li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.l %s0, 3, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i64 3, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @divi32li(i32 %a, i32 %b) {
 ; CHECK-LABEL: divi32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    divs.w.sx %s0, 3, %s0
+; CHECK-NEXT:    divs.w.sx %s0, 3, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = sdiv i32 3, %b
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @divu64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: divu64li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s0, 3, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i64 3, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @divu32li(i32 %a, i32 %b) {
 ; CHECK-LABEL: divu32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    divu.w %s0, 3, %s0
+; CHECK-NEXT:    divu.w %s0, 3, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = udiv i32 3, %b
   ret i32 %r
 }

llvm/test/CodeGen/VE/int_to_fp.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 ; Function Attrs: norecurse nounwind readnone
 define float @c2f(i8 signext %a) {
 ; CHECK-LABEL: c2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i8 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @s2f(i16 signext %a) {
 ; CHECK-LABEL: s2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i16 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @i2f(i32 %a) {
 ; CHECK-LABEL: i2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i32 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @l2f(i64 %a) {
 ; CHECK-LABEL: l2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    cvt.s.d %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i64 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @uc2f(i8 zeroext %a) {
 ; CHECK-LABEL: uc2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i8 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define float @us2f(i16 zeroext %a) {
 ; CHECK-LABEL: us2f:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.s.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i16 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
entry:
   %conv = uitofp i64 %a to float
   ret float %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @c2d(i8 signext %a) {
 ; CHECK-LABEL: c2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i8 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @s2d(i16 signext %a) {
 ; CHECK-LABEL: s2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i16 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @i2d(i32 %a) {
 ; CHECK-LABEL: i2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i32 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @l2d(i64 %a) {
 ; CHECK-LABEL: l2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    cvt.d.l %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = sitofp i64 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @uc2d(i8 zeroext %a) {
 ; CHECK-LABEL: uc2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i8 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @us2d(i16 zeroext %a) {
 ; CHECK-LABEL: us2d:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cvt.d.w %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %conv = uitofp i16 %a to double
   ret double %conv
 }
 
 ; Function Attrs: norecurse nounwind readnone

llvm/test/CodeGen/VE/left_shift.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %0, i8 signext %1) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sext i8 %0 to i32
   %4 = sext i8 %1 to i32
   %5 = shl i32 %3, %4
   %6 = trunc i32 %5 to i8
   ret i8 %6
 }
 
 define signext i16 @func2(i16 signext %0, i16 signext %1) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sext i16 %0 to i32
   %4 = sext i16 %1 to i32
   %5 = shl i32 %3, %4
   %6 = trunc i32 %5 to i16
   ret i16 %6
 }
 
 define i32 @func3(i32 %0, i32 %1) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = shl i32 %0, %1
   ret i32 %3
 }
 
 define i64 @func4(i64 %0, i64 %1) {
 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = shl i64 %0, %1
   ret i64 %3
 }
 
 define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = zext i8 %0 to i32
   %4 = zext i8 %1 to i32
   %5 = shl i32 %3, %4
   %6 = trunc i32 %5 to i8
   ret i8 %6
 }
 
 define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = zext i16 %0 to i32
   %4 = zext i16 %1 to i32
   %5 = shl i32 %3, %4
   %6 = trunc i32 %5 to i16
   ret i16 %6
 }
 
 define i32 @func8(i32 %0, i32 %1) {
 ; CHECK-LABEL: func8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = shl i32 %0, %1
   ret i32 %3
 }
 
 define i64 @func9(i64 %0, i64 %1) {
 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    sll %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = shl i64 %0, %1
   ret i64 %3
 }
 
 define signext i8 @func11(i8 signext %0) {
 ; CHECK-LABEL: func11:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i8 %0, 5
   ret i8 %2
 }
 
 define signext i16 @func12(i16 signext %0) {
 ; CHECK-LABEL: func12:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i16 %0, 5
   ret i16 %2
 }
 
 define i32 @func13(i32 %0) {
 ; CHECK-LABEL: func13:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i32 %0, 5
   ret i32 %2
 }
 
 define i64 @func14(i64 %0) {
 ; CHECK-LABEL: func14:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i64 %0, 5
   ret i64 %2
 }
 
 define zeroext i8 @func16(i8 zeroext %0) {
 ; CHECK-LABEL: func16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    lea %s1, 224
 ; CHECK-NEXT:    and %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i8 %0, 5
   ret i8 %2
 }
 
 define zeroext i16 @func17(i16 zeroext %0) {
 ; CHECK-LABEL: func17:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    lea %s1, 65504
 ; CHECK-NEXT:    and %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i16 %0, 5
   ret i16 %2
 }
 
 define i32 @func18(i32 %0) {
 ; CHECK-LABEL: func18:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i32 %0, 5
   ret i32 %2
 }
 
 define i64 @func19(i64 %0) {
 ; CHECK-LABEL: func19:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = shl i64 %0, 5
   ret i64 %2
 }
 

llvm/test/CodeGen/VE/max.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp uge i64 %0, %1
   %4 = select i1 %3, i64 %0, i64 %1
   ret i64 %4
 }
 
 define i32 @maxi32(i32, i32) {
 ; CHECK-LABEL: maxi32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    maxs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sgt i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define i32 @max2i32(i32, i32) {
 ; CHECK-LABEL: max2i32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    maxs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sge i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define i32 @maxu32(i32, i32) {
 ; CHECK-LABEL: maxu32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s2, %s0
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s2, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s1, %s0, %s2
+; CHECK-NEXT:    or %s0, 0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ugt i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define i32 @max2u32(i32, i32) {
 ; CHECK-LABEL: max2u32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s2, %s0
-; CHECK-NEXT:    cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s2, %s0, %s1
+; CHECK-NEXT:    cmov.w.ge %s1, %s0, %s2
+; CHECK-NEXT:    or %s0, 0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp uge i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {
 ; CHECK-LABEL: maxi1:

llvm/test/CodeGen/VE/min.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ule i64 %0, %1
   %4 = select i1 %3, i64 %0, i64 %1
   ret i64 %4
 }
 
 define i32 @mini32(i32, i32) {
 ; CHECK-LABEL: mini32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    mins.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp slt i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define i32 @min2i32(i32, i32) {
 ; CHECK-LABEL: min2i32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    mins.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sle i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define i32 @minu32(i32, i32) {
 ; CHECK-LABEL: minu32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s2, %s0
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s2, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s1, %s0, %s2
+; CHECK-NEXT:    or %s0, 0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ult i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define i32 @min2u32(i32, i32) {
 ; CHECK-LABEL: min2u32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s2, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s2, %s0
-; CHECK-NEXT:    cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s2, %s0, %s1
+; CHECK-NEXT:    cmov.w.le %s1, %s0, %s2
+; CHECK-NEXT:    or %s0, 0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ule i32 %0, %1
   %4 = select i1 %3, i32 %0, i32 %1
   ret i32 %4
 }
 
 define zeroext i1 @mini1(i1 zeroext, i1 zeroext) {
 ; CHECK-LABEL: mini1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    and %s2, %s1, %s0
 ; CHECK-NEXT:    cmov.w.ne %s2, %s1, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = xor i1 %0, true
   %4 = and i1 %3, %1
   %5 = select i1 %4, i1 %0, i1 %1
   ret i1 %5
 }

llvm/test/CodeGen/VE/multiply.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i8 %b, %a
   ret i8 %r
 }
 
 define signext i16 @func2(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i16 %b, %a
   ret i16 %r
 }
 
 define i32 @func3(i32 %a, i32 %b) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul nsw i32 %b, %a
   ret i32 %r
 }
 
 define i64 @func4(i64 %a, i64 %b) {
 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul nsw i64 %b, %a
   ret i64 %r
 }
 
 define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: func5:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i8 %b, %a
   ret i8 %r
 }
 
 define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i16 %b, %a
   ret i16 %r
 }
 
 define i32 @func7(i32 %a, i32 %b) {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i32 %b, %a
   ret i32 %r
 }
 
 define i64 @func8(i64 %a, i64 %b) {
 ; CHECK-LABEL: func8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, %s1, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i64 %b, %a
   ret i64 %r
 }
 
 define signext i8 @func9(i8 signext %a) {
 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i8 %a, 5
   ret i8 %r
 }
 
 define signext i16 @func10(i16 signext %a) {
 ; CHECK-LABEL: func10:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i16 %a, 5
   ret i16 %r
 }
 
 define i32 @func11(i32 %a) {
 ; CHECK-LABEL: func11:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul nsw i32 %a, 5
   ret i32 %r
 }
 
 define i64 @func12(i64 %a) {
 ; CHECK-LABEL: func12:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul nsw i64 %a, 5
   ret i64 %r
 }
 
 define zeroext i8 @func13(i8 zeroext %a) {
 ; CHECK-LABEL: func13:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i8 %a, 5
   ret i8 %r
 }
 
 define zeroext i16 @func14(i16 zeroext %a) {
 ; CHECK-LABEL: func14:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i16 %a, 5
   ret i16 %r
 }
 
 define i32 @func15(i32 %a) {
 ; CHECK-LABEL: func15:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    muls.w.sx %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i32 %a, 5
   ret i32 %r
 }
 
 define i64 @func16(i64 %a) {
 ; CHECK-LABEL: func16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    muls.l %s0, 5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = mul i64 %a, 5
   ret i64 %r
 }
 
 define i32 @func17(i32 %a) {
 ; CHECK-LABEL: func17:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 31
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = shl i32 %a, 31
   ret i32 %r
 }
 
 define i64 @func18(i64 %a) {
 ; CHECK-LABEL: func18:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s0, %s0, 31
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = shl nsw i64 %a, 31
   ret i64 %r
 }

llvm/test/CodeGen/VE/rem.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i64 %a, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @remi32(i32 %a, i32 %b) {
 ; CHECK-LABEL: remi32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 %a, %b
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remu64(i64 %a, i64 %b) {
 ; CHECK-LABEL: remu64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s2, %s0, %s1
 ; CHECK-NEXT:    muls.l %s1, %s2, %s1
 ; CHECK-NEXT:    subs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i64 %a, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @remu32(i32 %a, i32 %b) {
 ; CHECK-LABEL: remu32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i32 %a, %b
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i16 @remi16(i16 signext %a, i16 signext %b) {
 ; CHECK-LABEL: remi16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a32 = sext i16 %a to i32
   %b32 = sext i16 %b to i32
   %r32 = srem i32 %a32, %b32
   %r = trunc i32 %r32 to i16
   ret i16 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i16 @remu16(i16 zeroext %a, i16 zeroext %b) {
 ; CHECK-LABEL: remu16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i16 %a, %b
   ret i16 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define signext i8 @remi8(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: remi8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a32 = sext i8 %a to i32
   %b32 = sext i8 %b to i32
   %r32 = srem i32 %a32, %b32
   %r = trunc i32 %r32 to i8
   ret i8 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define zeroext i8 @remu8(i8 zeroext %a, i8 zeroext %b) {
 ; CHECK-LABEL: remu8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s2, %s0, %s1
 ; CHECK-NEXT:    muls.w.sx %s1, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i8 %a, %b
   ret i8 %r
 }
; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i64 %a, 3
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @remi32ri(i32 %a, i32 %b) {
 ; CHECK-LABEL: remi32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divs.w.sx %s1, %s0, (62)0
 ; CHECK-NEXT:    muls.w.sx %s1, 3, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 %a, 3
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remu64ri(i64 %a, i64 %b) {
 ; CHECK-LABEL: remu64ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s1, %s0, (62)0
 ; CHECK-NEXT:    muls.l %s1, 3, %s1
 ; CHECK-NEXT:    subs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i64 %a, 3
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @remu32ri(i32 %a, i32 %b) {
 ; CHECK-LABEL: remu32ri:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    divu.w %s1, %s0, (62)0
 ; CHECK-NEXT:    muls.w.sx %s1, 3, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i32 %a, 3
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remi64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: remi64li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divs.l %s0, 3, %s1
 ; CHECK-NEXT:    muls.l %s0, %s0, %s1
 ; CHECK-NEXT:    subs.l %s0, 3, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i64 3, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @remi32li(i32 %a, i32 %b) {
 ; CHECK-LABEL: remi32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    divs.w.sx %s1, 3, %s0
-; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
+; CHECK-NEXT:    divs.w.sx %s0, 3, %s1
+; CHECK-NEXT:    muls.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, 3, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = srem i32 3, %b
   ret i32 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @remu64li(i64 %a, i64 %b) {
 ; CHECK-LABEL: remu64li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    divu.l %s0, 3, %s1
 ; CHECK-NEXT:    muls.l %s0, %s0, %s1
 ; CHECK-NEXT:    subs.l %s0, 3, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i64 3, %b
   ret i64 %r
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i32 @remu32li(i32 %a, i32 %b) {
 ; CHECK-LABEL: remu32li:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s1, (0)1
-; CHECK-NEXT:    divu.w %s1, 3, %s0
-; CHECK-NEXT:    muls.w.sx %s0, %s1, %s0
+; CHECK-NEXT:    divu.w %s0, 3, %s1
+; CHECK-NEXT:    muls.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    subs.w.sx %s0, 3, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = urem i32 3, %b
   ret i32 %r
 }

llvm/test/CodeGen/VE/right_shift.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %0, i8 signext %1) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sext i8 %0 to i32
   %4 = sext i8 %1 to i32
   %5 = ashr i32 %3, %4
   %6 = trunc i32 %5 to i8
   ret i8 %6
 }
 
 define signext i16 @func2(i16 signext %0, i16 signext %1) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sext i16 %0 to i32
   %4 = sext i16 %1 to i32
   %5 = ashr i32 %3, %4
   %6 = trunc i32 %5 to i16
   ret i16 %6
 }
 
 define i32 @func3(i32 %0, i32 %1) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = ashr i32 %0, %1
   ret i32 %3
 }
 
 define i64 @func4(i64 %0, i64 %1) {
 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    sra.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = ashr i64 %0, %1
   ret i64 %3
 }
 
 define zeroext i8 @func7(i8 zeroext %0, i8 zeroext %1) {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = zext i8 %0 to i32
   %4 = zext i8 %1 to i32
   %5 = lshr i32 %3, %4
   %6 = trunc i32 %5 to i8
   ret i8 %6
 }
 
 define zeroext i16 @func8(i16 zeroext %0, i16 zeroext %1) {
 ; CHECK-LABEL: func8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, %s1
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = zext i16 %0 to i32
   %4 = zext i16 %1 to i32
   %5 = lshr i32 %3, %4
   %6 = trunc i32 %5 to i16
   ret i16 %6
 }
 
 define i32 @func9(i32 %0, i32 %1) {
 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = lshr i32 %0, %1
   ret i32 %3
 }
 
 define i64 @func10(i64 %0, i64 %1) {
 ; CHECK-LABEL: func10:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    srl %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = lshr i64 %0, %1
   ret i64 %3
 }
 
 define signext i8 @func12(i8 signext %0) {
 ; CHECK-LABEL: func12:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = ashr i8 %0, 5
   ret i8 %2
 }
 
 define signext i16 @func13(i16 signext %0) {
 ; CHECK-LABEL: func13:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = ashr i16 %0, 5
   ret i16 %2
 }
 
 define i32 @func14(i32 %0) {
 ; CHECK-LABEL: func14:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = ashr i32 %0, 5
   ret i32 %2
 }
 
 define i64 @func15(i64 %0) {
 ; CHECK-LABEL: func15:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sra.l %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = ashr i64 %0, 5
   ret i64 %2
 }
 
 define zeroext i8 @func17(i8 zeroext %0) {
 ; CHECK-LABEL: func17:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, 5
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = lshr i8 %0, 5
   ret i8 %2
 }
 
 define zeroext i16 @func18(i16 zeroext %0) {
 ; CHECK-LABEL: func18:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, 5
 ; CHECK-NEXT:    adds.w.zx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = lshr i16 %0, 5
   ret i16 %2
 }
 
 define i32 @func19(i32 %0) {
 ; CHECK-LABEL: func19:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = lshr i32 %0, 5
   ret i32 %2
 }
 
 define i64 @func20(i64 %0) {
 ; CHECK-LABEL: func20:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    srl %s0, %s0, 5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %2 = lshr i64 %0, 5
   ret i64 %2
 }
 

llvm/test/CodeGen/VE/rotl.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i64 @func1(i64 %a, i32 %b) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    sll %s2, %s0, %s1
 ; CHECK-NEXT:    lea %s3, 64
 ; CHECK-NEXT:    subs.w.sx %s1, %s3, %s1
 ; CHECK-NEXT:    srl %s0, %s0, %s1
 ; CHECK-NEXT:    or %s0, %s0, %s2
 ; CHECK-NEXT:    or %s11, 0, %s9
   %b64 = zext i32 %b to i64
   %a.sl = shl i64 %a, %b64
   %b.inv = sub nsw i32 64, %b
   %b.inv64 = zext i32 %b.inv to i64
   %a.sr = lshr i64 %a, %b.inv64
   %r = or i64 %a.sr, %a.sl
   ret i64 %r
 }
 
 define i32 @func2(i32 %a, i32 %b) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    sla.w.sx %s2, %s0, %s1
 ; CHECK-NEXT:    subs.w.sx %s1, 32, %s1
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    srl %s0, %s0, %s1
 ; CHECK-NEXT:    or %s0, %s0, %s2
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.sl = shl i32 %a, %b
   %b.inv = sub nsw i32 32, %b
   %a.sr = lshr i32 %a, %b.inv
   %r = or i32 %a.sr, %a.sl
   ret i32 %r
 }
 

llvm/test/CodeGen/VE/rotr.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i64 @func1(i64 %a, i32 %b) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
 ; CHECK-NEXT:    srl %s2, %s0, %s1
 ; CHECK-NEXT:    lea %s3, 64
 ; CHECK-NEXT:    subs.w.sx %s1, %s3, %s1
 ; CHECK-NEXT:    sll %s0, %s0, %s1
 ; CHECK-NEXT:    or %s0, %s0, %s2
 ; CHECK-NEXT:    or %s11, 0, %s9
   %b64 = zext i32 %b to i64
   %a.lr = lshr i64 %a, %b64
   %b.inv = sub nsw i32 64, %b
   %b.inv64 = zext i32 %b.inv to i64
   %a.sl = shl i64 %a, %b.inv64
   %r = or i64 %a.sl, %a.lr
   ret i64 %r
 }
 
 define i32 @func2(i32 %a, i32 %b) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    and %s2, %s0, (32)0
 ; CHECK-NEXT:    srl %s2, %s2, %s1
 ; CHECK-NEXT:    subs.w.sx %s1, 32, %s1
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s0, %s0, %s2
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.lr = lshr i32 %a, %b
   %b.inv = sub nsw i32 32, %b
   %a.sl = shl i32 %a, %b.inv
   %r = or i32 %a.sl, %a.lr
   ret i32 %r
 }

llvm/test/CodeGen/VE/select.ll

 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = select i1 %0, i64 %1, i64 %2
   ret i64 %4
 }
 
 define i32 @selecti32(i1 zeroext, i32, i32) {
 ; CHECK-LABEL: selecti32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s3, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s2, (0)1
-; CHECK-NEXT:    cmov.w.ne %s0, %s1, %s3
+; CHECK-NEXT:    cmov.w.ne %s2, %s1, %s0
+; CHECK-NEXT:    or %s0, 0, %s2
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = select i1 %0, i32 %1, i32 %2
   ret i32 %4
 }
 
 define zeroext i1 @selecti1(i1 zeroext, i1 zeroext, i1 zeroext) {
 ; CHECK-LABEL: selecti1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
 ; CHECK-NEXT:    cmov.w.ne %s2, %s1, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s2, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %4 = select i1 %0, i1 %1, i1 %2
   ret i1 %4
 }

llvm/test/CodeGen/VE/selectccf32c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i16 %0, %1
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }
 
 define float @selectccsgti32(i32, i32, float, float) {
 ; CHECK-LABEL: selectccsgti32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i32 %0, %1
   %6 = select i1 %5, float %2, float %3
   ret float %6
 }

llvm/test/CodeGen/VE/selectccf64c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i16 %0, %1
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }
 
 define double @selectccsgti32(i32, i32, double, double) {
 ; CHECK-LABEL: selectccsgti32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i32 %0, %1
   %6 = select i1 %5, double %2, double %3
   ret double %6
 }

llvm/test/CodeGen/VE/selectcci32.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i32 @selectcceq(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectcceq:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.eq %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.eq %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccne(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccne:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.ne %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.ne %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ne i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgt(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsgt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsge(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.ge %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sge i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccslt(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccslt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp slt i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsle(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsle:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.le %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sle i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccugt(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccugt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ugt i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccuge(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccuge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.ge %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp uge i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccult(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccult:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ult i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccule(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccule:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.le %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ule i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccugt2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccugt2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ugt i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccuge2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccuge2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.ge %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.ge %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp uge i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccult2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccult2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ult i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccule2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccule2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.le %s0, %s2, %s1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.le %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ule i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }

llvm/test/CodeGen/VE/selectcci32c.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i32 @selectccsgti8(i8, i8, i32, i32) {
 ; CHECK-LABEL: selectccsgti8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s1, %s1, 56
 ; CHECK-NEXT:    sra.l %s1, %s1, 56
 ; CHECK-NEXT:    sll %s0, %s0, 56
-; CHECK-NEXT:    sra.l %s4, %s0, 56
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    sra.l %s0, %s0, 56
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i8 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgti16(i16, i16, i32, i32) {
 ; CHECK-LABEL: selectccsgti16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    sll %s1, %s1, 48
 ; CHECK-NEXT:    sra.l %s1, %s1, 48
 ; CHECK-NEXT:    sll %s0, %s0, 48
-; CHECK-NEXT:    sra.l %s4, %s0, 48
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    sra.l %s0, %s0, 48
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i16 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgti32(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsgti32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s4, %s1
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i32 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgti64(i64, i64, i32, i32) {
 ; CHECK-LABEL: selectccsgti64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s4, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s3, (0)1
 ; CHECK-NEXT:    cmps.l %s0, %s0, %s1
-; CHECK-NEXT:    cmov.l.gt %s2, %s4, %s0
-; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i64 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgti128(i128, i128, i32, i32) {
 ; CHECK-LABEL: selectccsgti128:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s6, %s4, (0)1
-; CHECK-NEXT:    adds.w.sx %s4, %s5, (0)1
-; CHECK-NEXT:    or %s5, 0, (0)1
+; CHECK-NEXT:    or %s6, 0, (0)1
 ; CHECK-NEXT:    cmps.l %s1, %s1, %s3
-; CHECK-NEXT:    or %s3, 0, %s5
+; CHECK-NEXT:    or %s3, 0, %s6
 ; CHECK-NEXT:    cmov.l.gt %s3, (63)0, %s1
 ; CHECK-NEXT:    cmpu.l %s0, %s0, %s2
-; CHECK-NEXT:    cmov.l.gt %s5, (63)0, %s0
-; CHECK-NEXT:    cmov.l.eq %s3, %s5, %s1
+; CHECK-NEXT:    cmov.l.gt %s6, (63)0, %s0
+; CHECK-NEXT:    cmov.l.eq %s3, %s6, %s1
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s3, %s0
-; CHECK-NEXT:    cmov.w.ne %s4, %s6, %s0
-; CHECK-NEXT:    or %s0, 0, %s4
+; CHECK-NEXT:    cmov.w.ne %s5, %s4, %s0
+; CHECK-NEXT:    or %s0, 0, %s5
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i128 %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccogtf32(float, float, i32, i32) {
 ; CHECK-LABEL: selectccogtf32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s4, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s3, (0)1
 ; CHECK-NEXT:    fcmp.s %s0, %s0, %s1
-; CHECK-NEXT:    cmov.s.gt %s2, %s4, %s0
-; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    cmov.s.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = fcmp ogt float %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccogtf64(double, double, i32, i32) {
 ; CHECK-LABEL: selectccogtf64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s4, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s3, (0)1
 ; CHECK-NEXT:    fcmp.d %s0, %s0, %s1
-; CHECK-NEXT:    cmov.d.gt %s2, %s4, %s0
-; CHECK-NEXT:    or %s0, 0, %s2
+; CHECK-NEXT:    cmov.d.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = fcmp ogt double %0, %1
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 

llvm/test/CodeGen/VE/selectcci32i.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i32 @selectcceq(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectcceq:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.eq %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.eq %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp eq i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccne(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccne:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.ne %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.ne %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ne i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsgt(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsgt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsge(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 11, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 11, (0)1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sge i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccslt(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccslt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp slt i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccsle(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccsle:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 13, (0)1
-; CHECK-NEXT:    cmps.w.sx %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 13, (0)1
+; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sle i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccugt(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccugt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ugt i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccuge(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccuge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 11, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 11, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp uge i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccult(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccult:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ult i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccule(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccule:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 13, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 13, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ule i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccugt2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccugt2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ugt i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccuge2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccuge2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 11, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.gt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 11, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp uge i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccult2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccult2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 12, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 12, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ult i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }
 
 define i32 @selectccule2(i32, i32, i32, i32) {
 ; CHECK-LABEL: selectccule2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s0, (0)1
-; CHECK-NEXT:    adds.w.sx %s2, %s2, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s3, (0)1
-; CHECK-NEXT:    or %s3, 13, (0)1
-; CHECK-NEXT:    cmpu.w %s1, %s1, %s3
-; CHECK-NEXT:    cmov.w.lt %s0, %s2, %s1
+; CHECK-NEXT:    or %s1, 13, (0)1
+; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
+; CHECK-NEXT:    cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp ule i32 %0, 12
   %6 = select i1 %5, i32 %2, i32 %3
   ret i32 %6
 }

llvm/test/CodeGen/VE/selectcci64c.ll

; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i16 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }
 
 define i64 @selectccsgti32(i32, i32, i64, i64) {
 ; CHECK-LABEL: selectccsgti32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    cmov.w.gt %s3, %s2, %s0
 ; CHECK-NEXT:    or %s0, 0, %s3
 ; CHECK-NEXT:    or %s11, 0, %s9
   %5 = icmp sgt i32 %0, %1
   %6 = select i1 %5, i64 %2, i64 %3
   ret i64 %6
 }

llvm/test/CodeGen/VE/setcci32.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define zeroext i1 @setcceq(i32, i32) {
 ; CHECK-LABEL: setcceq:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.eq %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp eq i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccne(i32, i32) {
 ; CHECK-LABEL: setccne:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.ne %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ne i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccugt(i32, i32) {
 ; CHECK-LABEL: setccugt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.gt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ugt i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccuge(i32, i32) {
 ; CHECK-LABEL: setccuge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.ge %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp uge i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccult(i32, i32) {
 ; CHECK-LABEL: setccult:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.lt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ult i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccule(i32, i32) {
 ; CHECK-LABEL: setccule:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.le %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ule i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccsgt(i32, i32) {
 ; CHECK-LABEL: setccsgt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.gt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sgt i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccsge(i32, i32) {
 ; CHECK-LABEL: setccsge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.ge %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sge i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccslt(i32, i32) {
 ; CHECK-LABEL: setccslt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.lt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp slt i32 %0, %1
   ret i1 %3
 }
 
 define zeroext i1 @setccsle(i32, i32) {
 ; CHECK-LABEL: setccsle:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.le %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sle i32 %0, %1
   ret i1 %3
 }

llvm/test/CodeGen/VE/setcci32i.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define zeroext i1 @setcceq(i32, i32) {
 ; CHECK-LABEL: setcceq:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 12, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.eq %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp eq i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccne(i32, i32) {
 ; CHECK-LABEL: setccne:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 12, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.ne %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ne i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccugt(i32, i32) {
 ; CHECK-LABEL: setccugt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 12, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.gt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ugt i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccuge(i32, i32) {
 ; CHECK-LABEL: setccuge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 11, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.gt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp uge i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccult(i32, i32) {
 ; CHECK-LABEL: setccult:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 12, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.lt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ult i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccule(i32, i32) {
 ; CHECK-LABEL: setccule:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 13, (0)1
 ; CHECK-NEXT:    cmpu.w %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.lt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp ule i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccsgt(i32, i32) {
 ; CHECK-LABEL: setccsgt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 12, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.gt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sgt i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccsge(i32, i32) {
 ; CHECK-LABEL: setccsge:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 11, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.gt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sge i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccslt(i32, i32) {
 ; CHECK-LABEL: setccslt:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 12, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.lt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp slt i32 %0, 12
   ret i1 %3
 }
 
 define zeroext i1 @setccsle(i32, i32) {
 ; CHECK-LABEL: setccsle:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    or %s1, 13, (0)1
 ; CHECK-NEXT:    cmps.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s1, 0, (0)1
 ; CHECK-NEXT:    cmov.w.lt %s1, (63)0, %s0
 ; CHECK-NEXT:    adds.w.zx %s0, %s1, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = icmp sle i32 %0, 12
   ret i1 %3
 }

llvm/test/CodeGen/VE/subtraction.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %0, i8 signext %1) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i8 %0, %1
   ret i8 %3
 }
 
 define signext i16 @func2(i16 signext %0, i16 signext %1) {
 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i16 %0, %1
   ret i16 %3
 }
 
 define i32 @func3(i32 %0, i32 %1) {
 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub nsw i32 %0, %1
   ret i32 %3
 }
 
 define i64 @func4(i64 %0, i64 %1) {
 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub nsw i64 %0, %1
   ret i64 %3
 }
 
 define zeroext i8 @func6(i8 zeroext %0, i8 zeroext %1) {
 ; CHECK-LABEL: func6:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i8 %0, %1
   ret i8 %3
 }
 
 define zeroext i16 @func7(i16 zeroext %0, i16 zeroext %1) {
 ; CHECK-LABEL: func7:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i16 %0, %1
   ret i16 %3
 }
 
 define i32 @func8(i32 %0, i32 %1) {
 ; CHECK-LABEL: func8:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s1, %s1, (0)1
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    subs.w.sx %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i32 %0, %1
   ret i32 %3
 }
 
 define i64 @func9(i64 %0, i64 %1) {
 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    subs.l %s0, %s0, %s1
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = sub i64 %0, %1
   ret i64 %3
 }
 
 define signext i8 @func13(i8 signext %0, i8 signext %1) {
 ; CHECK-LABEL: func13:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 56
 ; CHECK-NEXT:    sra.l %s0, %s0, 56
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i8 %0, -5
   ret i8 %3
 }
 
 define signext i16 @func14(i16 signext %0, i16 signext %1) {
 ; CHECK-LABEL: func14:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    sll %s0, %s0, 48
 ; CHECK-NEXT:    sra.l %s0, %s0, 48
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i16 %0, -5
   ret i16 %3
 }
 
 define i32 @func15(i32 %0, i32 %1) {
 ; CHECK-LABEL: func15:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add nsw i32 %0, -5
   ret i32 %3
 }
 
 define i64 @func16(i64 %0, i64 %1) {
 ; CHECK-LABEL: func16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, -5(, %s0)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add nsw i64 %0, -5
   ret i64 %3
 }
 
 define zeroext i8 @func18(i8 zeroext %0, i8 zeroext %1) {
 ; CHECK-LABEL: func18:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (56)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i8 %0, -5
   ret i8 %3
 }
 
 define zeroext i16 @func19(i16 zeroext %0, i16 zeroext %1) {
 ; CHECK-LABEL: func19:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    and %s0, %s0, (48)0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i16 %0, -5
   ret i16 %3
 }
 
 define i32 @func20(i32 %0, i32 %1) {
 ; CHECK-LABEL: func20:
 ; CHECK:       .LBB{{[0-9]+}}_2:
-; CHECK-NEXT:    adds.w.sx %s0, %s0, (0)1
 ; CHECK-NEXT:    adds.w.sx %s0, -5, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %3 = add i32 %0, -5
   ret i32 %3
 }
 
 define i64 @func21(i64 %0, i64 %1) {
 ; CHECK-LABEL: func21: