[PowerPC] Add Support for PPC750 Paired Single ext

[DarkKirb]

Summary

The Paired Single extension is a extension to the PowerPC ISA and is
found on the PPC 750CL-series processors. These processors were most
notably used in Nintendo home consoles.

The Paired Single extension adds a simple version of SIMD to the
architecture. Each SIMD Vector contains 2 32-bit floats. Most of the
floating-point instructions supported by the 750CL are also implemented
in the Paired Single extension.

This initial patch adds the following intrinsic declarations (in

alphabetic order):

v2f32 ppc_paired_l(const v2f32 *src, i1 word, i8 gqr);
void  ppc_paired_st(v2f32 val, v2f32 *dst, i1 word, i8 gqr);
v2f32 ppc_paired_madds0(v2f32 a, v2f32 b, v2f32 c);
v2f32 ppc_paired_madds1(v2f32 a, v2f32 b, v2f32 c);
v2f32 ppc_paired_merge00(v2f32 a, v2f32 b);
v2f32 ppc_paired_merge01(v2f32 a, v2f32 b);
v2f32 ppc_paired_merge10(v2f32 a, v2f32 b);
v2f32 ppc_paired_merge11(v2f32 a, v2f32 b);
v2f32 ppc_paired_muls0(v2f32 a, v2f32 b);
v2f32 ppc_paired_muls1(v2f32 a, v2f32 b);
v2f32 ppc_paired_sel(v2f32 sel, v2f32 a, v2f32 bit);
v2f32 ppc_paired_sum0(v2f32 a, v2f32 b, v2f32 c);
v2f32 ppc_paired_sum1(v2f32 a, v2f32 b, v2f32 c);

• ppc_paired_l maps to psq_l, psq_lx, psq_lu or psq_lux. It loads the paired single from the memory location
• ppc_paired_st maps to psq_st, psq_stx, psq_stu, or psq_stux. It stores the paired single to the memory location.
• ppc_paired_madds0 and ppc_paired_madds1 are multiply-accumulate a
  • c + b with the 1st or 2nd element of c being used for both elements respectively.
• ppc_paired_merge[01][01] merges the 1st/2nd element of the first vector with the 1st/2nd element of the second vector and creates a new vector
• ppc_paired_muls[01] multiply a with the 1st/2nd element of b (depending on the name)
• ppc_paired_sel is a dynamic variant of the merge* functions. It will take an element of vector a if the corresponding control entry is smaller than 0 and will use b otherwise
• ppc_paired_sum[01] will replace the 1st/2nd element of c with the sum of the first element of a and the second element of b

[PowerPC] Add Intrinsic for broadway-exclusive dcbz_l

A feature that only exists on the Nintendo Versions of the 750CL is the
locked cache. To support it one instruction was added: dcbz_l.

NOTE: this instruction is not the same as dcbzl. They have different instruction encodings and also different semantics. It works similar to dcbz, however it requires the locked cache to be enabled.

[PowerPC] Add assembly support for Paired Single

In particular, this commit adds support for the 32 2x32 bit "paired
single" point registers, makes changes to the calling convention to
support paired singles and adds all of the new instructions.

The ABI is not standardized everywhere. As far as I can tell there is no
standard ABI. Other compilers appear to not support passing paired
single types as arguments or to even interact with the extension at all
outside of inline assembly.

This calling convention is based on the Floating Point cc, meaning that
the first 8 arguments are stored in psf1-8 and 14-31 are callee-saved
registers. Another thing not found in the code is that GQR0 (SPR 912)
has to be set to 0. There is no GQR register class because the GQRs
can not be read or set from userspace.

Special thanks to Github user Tilka who created a similar, but much smaller patchset in 2014.

I'm currently working on getting codegen for the extension working. Many instructions are already working, however it is quite useless at the current stage since loads and stores are not working.

[DarkKirb]

This comment was removed by DarkKirb.

[DarkKirb]

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[DarkKirb]

[PowerPC] Add Test for Paired Single Decoding

This has uncovered multiple bugs with my previous implementation, namely that
ps_res and ps_frsqte had the wrong opcode and that the decoding for
immediate-offset loads and stores in ps_l* and ps_st* caused internal compiler
errors.

I couldn't reuse the logic from other immediate-offset code because

1. The register and the offset field are not right next to each other
2. The currently existing memri* asm operands are not 12 bit with unaligned offsets.

This commit also fixes the test suite for powerpc as it puts the new
instructions into a separate namespace (called Paired).

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

bool isU7ImmX4() const { return Kind == Immediate &&
                                   (getImm() & 3) == 0; }
   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
   bool isU8ImmX8() const { return Kind == Immediate &&
                                   isUInt<8>(getImm()) &&
                                   (getImm() & 7) == 0; }
 
   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
+  bool isS12Imm() const {
+    return Kind == Expression || (Kind == Immediate && isInt<12>(getImm()));
+  }
   bool isU16Imm() const {
     switch (Kind) {
       case Expression:
         return true;
       case Immediate:
       case ContextImmediate:
         return isUInt<16>(getImmU16Context());
       default:

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 
   if (STI.getFeatureBits()[PPC::FeatureSPE]) {
     DecodeStatus result =
         decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
     if (result != MCDisassembler::Fail)
       return result;
   }
 
+  if (STI.getFeatureBits()[PPC::FeaturePaired]) {
+    DecodeStatus result = decodeInstruction(DecoderTablePairedSingle32, MI,
+                                            Inst, Address, this, STI);
+    if (result != MCDisassembler::Fail)
+      return result;
+  }
+
   return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
 }

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class PSQForm_xw<bits<6> op, dag OOL, dag IOL, string asmstr,
   let Inst{25-30} = op;
   let Inst{31} = 0; // no record mode supported
 }
 
 class PSQForm_dw<bits<6> op, dag OOL, dag IOL, string asmstr,
                 InstrItinClass itin, list<dag> pattern>
     :I<op, OOL, IOL, asmstr, itin> {
   bits<5> D;
-  bits<5> A;
   bit W;
   bits<3> I;
   bits<12> d;
+  bits<5> A;
 
   let Pattern = pattern;
 
   let Inst{6-10} = D;
   let Inst{11-15} = A;
   let Inst{16} = W;
   let Inst{17-19} = I;
   let Inst{20-31} = d;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 }
 def PPCDispSPE2Operand : AsmOperandClass {
  let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
  let RenderMethod = "addImmOperands";
 }
 def dispSPE2 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE2Operand;
 }
+def PPCDispRID12Operand : AsmOperandClass {
+ let Name = "DispRID12"; let PredicateMethod = "isS12Imm";
+ let RenderMethod = "addImmOperands";
+}
+def dispRID12 : Operand<iPTR> {
+  let ParserMatchClass = PPCDispRID12Operand;
+}
 
 def memri : Operand<iPTR> {
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getMemRIEncoding";
   let DecoderMethod = "decodeMemRIOperands";
 }
 def memrr : Operand<iPTR> {
def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
   let DecoderMethod = "decodeSPE4Operands";
 }
 def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getSPE2DisEncoding";
   let DecoderMethod = "decodeSPE2Operands";
 }
+def memrid12 : Operand<iPTR> { // Paired Single displacement where imm is 12 bits wide.
+  let PrintMethod = "printMemRegImm";
+  let MIOperandInfo = (ops dispRID12:$imm, ptr_rc_nor0:$reg);
+}
 
 // A single-register address. This is used with the SjLj
 // pseudo-instructions which translates to LD/LWZ.  These instructions requires
 // G8RC_NOX0 registers.
 def memr : Operand<iPTR> {
   let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
 }
 def PPCTLSRegOperand : AsmOperandClass {

llvm/lib/Target/PowerPC/PPCInstrPaired.td

def NAME : PSForm_ad0b0<xo, OOL, IOL,
                             pattern>, RecFormRel;
     let Defs = [CR1] in
     def _rec : PSForm_ad0b0<xo, OOL, IOL,
                             !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                             []>, isRecordForm, RecFormRel;
   }
 }
 
+let DecoderNamespace = "PairedSingle" in {
     let Predicates = [HasPaired] in {
-    // Technically not part of the 750cl since it is a proprietary instruction
-    // found on the Nintendo versions of the chip.
         def DCBZ_L : PSForm_x0ab<1014, (outs), (ins memrr:$dst), "dcbz_l $dst",
                                 IIC_LdStDCBF, [(int_ppc_broadway_dcbz_l xoaddr:$dst)]>;
 
-    def PSQ_L : PSQForm_dw<56, (outs psrc:$fD), (ins memri:$src, u1imm:$W, u3imm:$I),
+        def PSQ_L : PSQForm_dw<56, (outs psrc:$fD), (ins memrid12:$src, u1imm:$W, u3imm:$I),
                               "psq_l $fD, $src, $W, $I", IIC_LdStLoad, []>;
 
         def PSQ_LU : PSQForm_dw<57, (outs psrc:$fD, ptr_rc_nor0:$ea_result),
-                            (ins memri:$src, u1imm:$W, u3imm:$I),
+                                (ins memrid12:$src, u1imm:$W, u3imm:$I),
                                 "psq_lu $fD, $src, $W, $I", IIC_LdStLoadUpd, []>,
                                 RegConstraint<"$src.reg = $ea_result">,
                                 NoEncode<"$ea_result">;
         def PSQ_LX : PSQForm_xw<6, (outs psrc:$fD), (ins memrr:$src, u1imm:$W, u3imm:$I),
                                 "psq_lx $fD, $src, $W, $I", IIC_LdStLoad, []>;
         def PSQ_LUX : PSQForm_xw<38, (outs psrc:$fD, ptr_rc_nor0:$ea_result),
                                 (ins memrr:$src, u1imm:$W, u3imm:$I),
                                 "psq_lux $fD, $src, $W, $I", IIC_LdStLoad, []>,
                                 RegConstraint<"$src.ptrreg = $ea_result">,
                                 NoEncode<"$ea_result">;
 
-    def PSQ_ST : PSQForm_dw<60, (outs), (ins psrc:$fD, memri:$dst, u1imm:$W, u3imm:$I),
+        def PSQ_ST : PSQForm_dw<60, (outs), (ins psrc:$fD, memrid12:$dst, u1imm:$W, u3imm:$I),
                                 "psq_st $fD, $dst, $W, $I", IIC_LdStStore, []>;
 
         def PSQ_STU : PSQForm_dw<61, (outs ptr_rc_nor0:$ea_result),
-                             (ins psrc:$fD, memri:$dst, u1imm:$W, u3imm:$I),
+                                (ins psrc:$fD, memrid12:$dst, u1imm:$W, u3imm:$I),
                                 "psq_stu $fD, $dst, $W, $I", IIC_LdStSTU, []>,
                                 RegConstraint<"$dst.reg = $ea_result">,
                                 NoEncode<"$ea_result">;
 
         def PSQ_STX : PSQForm_xw<7, (outs), (ins psrc:$fD, memrr:$dst, u1imm:$W, u3imm:$I),
                                 "psq_stx $fD, $dst, $W, $I", IIC_LdStStore, []>;
 
         def PSQ_STUX : PSQForm_xw<39, (outs ptr_rc_nor0:$ea_result),
                                   (ins psrc:$fD, memrr:$dst, u1imm:$W, u3imm:$I),
                                   "psq_stux $fD, $dst, $W, $I", IIC_LdStSTUX, []>,
                                   RegConstraint<"$dst.ptrreg = $ea_result">,
                                   NoEncode<"$ea_result">;
 
         defm PS_ABS : PSForm_xd0br<264, (outs psrc:$fD), (ins psrc:$fB),
                                     "ps_abs", "$fD, $fB", IIC_FPGeneral,
                                     [(set v2f32:$fD, (fabs v2f32:$fB))]>;
 
         defm PS_ADD : PSForm_adab0r<21, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                     "ps_add", "$fD, $fA, $fB", IIC_FPAddSub,
                                     [(set v2f32:$fD, (fadd v2f32:$fA, v2f32:$fB))]>;
 
         def PS_CMPU0 : PSForm_xcrab<0, 0, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
                                     "ps_cmpu0 $crD, $fA, $fB", IIC_FPCompare, []>;
         def PS_CMPU1 : PSForm_xcrab<0, 1, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
                                     "ps_cmpu1 $crD, $fA, $fB", IIC_FPCompare, []>;
         def PS_CMPO0 : PSForm_xcrab<1, 0, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
                                     "ps_cmpo0 $crD, $fA, $fB", IIC_FPCompare, []>;
         def PS_CMPO1 : PSForm_xcrab<1, 1, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
                                     "ps_cmpo1 $crD, $fA, $fB", IIC_FPCompare, []>;
 
         defm PS_DIV : PSForm_adab0r<18, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                     "ps_div", "$fD, $fA, $fB", IIC_FPDivS,
                                     [(set v2f32:$fD, (fdiv v2f32:$fA, v2f32:$fB))]>;
 
         defm PS_MADD : PSForm_adabcr<29, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                     "ps_madd", "$fD, $fA, $fC, $fB", IIC_FPFused,
                                     [(set v2f32:$fD, (fadd (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB))]>;
 
         defm PS_MADDS0 : PSForm_adabcr<14, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                       "ps_madds0", "$fD, $fA, $fC, $fB", IIC_FPFused,
                                       []>;
 
         defm PS_MADDS1 : PSForm_adabcr<15, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                       "ps_madds1", "$fD, $fA, $fC, $fB", IIC_FPFused,
                                       []>;
         defm PS_MERGE00 : PSForm_xdabr<528, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                       "ps_merge00", "$fD, $fA, $fB", IIC_FPGeneral,
                                       []>;
         defm PS_MERGE01 : PSForm_xdabr<560, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                       "ps_merge01", "$fD, $fA, $fB", IIC_FPGeneral,
                                       []>;
         defm PS_MERGE10 : PSForm_xdabr<592, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                       "ps_merge10", "$fD, $fA, $fB", IIC_FPGeneral,
                                       []>;
         defm PS_MERGE11 : PSForm_xdabr<624, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                       "ps_merge11", "$fD, $fA, $fB", IIC_FPGeneral,
                                       []>;
         defm PS_MR : PSForm_xd0br<72, (outs psrc:$fD), (ins psrc:$fB),
                                       "ps_mr", "$fD, $fB", IIC_FPGeneral,
                                       [(set v2f32:$fD, v2f32:$fB)]>;
 
         defm PS_MSUB : PSForm_adabcr<28, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                     "ps_msub", "$fD, $fA, $fC, $fB", IIC_FPFused,
                                     [(set v2f32:$fD, (fsub (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB))]>;
 
         defm PS_MUL : PSForm_ada0cr<25, (outs psrc:$fD), (ins psrc:$fA, psrc:$fC),
                                     "ps_mul", "$fD, $fA, $fC", IIC_FPFused,
                                     [(set v2f32:$fD, (fmul v2f32:$fA, v2f32:$fC))]>;
 
         defm PS_MULS0 : PSForm_ada0cr<12, (outs psrc:$fD), (ins psrc:$fA, psrc:$fC),
                                     "ps_muls0", "$fD, $fA, $fC", IIC_FPFused, []>;
         defm PS_MULS1 : PSForm_ada0cr<13, (outs psrc:$fD), (ins psrc:$fA, psrc:$fC),
                                     "ps_muls1", "$fD, $fA, $fC", IIC_FPFused, []>;
 
         defm PS_NABS : PSForm_xd0br<136, (outs psrc:$fD), (ins psrc:$fB),
                                     "ps_nabs", "$fD, $fB", IIC_FPGeneral,
                                     [(set v2f32:$fD, (fneg (fabs v2f32:$fB)))]>;
 
         defm PS_NEG : PSForm_xd0br<40, (outs psrc:$fD), (ins psrc:$fB),
                                     "ps_neg", "$fD, $fB", IIC_FPGeneral,
                                     [(set v2f32:$fD, (fneg v2f32:$fB))]>;
 
         defm PS_NMADD : PSForm_adabcr<31, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                     "ps_nmadd", "$fD, $fA, $fC, $fB", IIC_FPFused,
                                     [(set v2f32:$fD, (fneg (fadd (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB)))]>;
 
        defm PS_NMSUB : PSForm_adabcr<30, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                     "ps_nmsub", "$fD, $fA, $fC, $fB", IIC_FPFused,
                                     [(set v2f32:$fD, (fneg (fsub (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB)))]>;
 
         defm PS_RES : PSForm_ad0b0r<24, (outs psrc:$fD), (ins psrc:$fB),
                                     "ps_res", "$fD, $fB", IIC_FPGeneral,
                                     [(set v2f32:$fD, (PPCfre v2f32:$fB))]>;
 
-    defm PS_RSQRTE : PSForm_ad0b0r<24, (outs psrc:$fD), (ins psrc:$fB),
+        defm PS_RSQRTE : PSForm_ad0b0r<26, (outs psrc:$fD), (ins psrc:$fB),
                                       "ps_rsqrte", "$fD, $fB", IIC_FPGeneral,
                                       [(set v2f32:$fD, (PPCfrsqrte v2f32:$fB))]>;
 
       defm PS_SEL : PSForm_adabcr<23, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                   "ps_sel", "$fD, $fA, $fC, $fB", IIC_FPGeneral,
                                   []>;
 
         defm PS_SUB : PSForm_adab0r<20, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
                                     "ps_sub", "$fD, $fA, $fB", IIC_FPAddSub,
                                     [(set v2f32:$fD, (fsub v2f32:$fA, v2f32:$fB))]>;
 
        defm PS_SUM0 : PSForm_adabcr<10, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                     "ps_sum0", "$fD, $fA, $fC, $fB", IIC_FPAddSub,
                                     []>;
       defm PS_SUM1 : PSForm_adabcr<11, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
                                     "ps_sum1", "$fD, $fA, $fC, $fB", IIC_FPAddSub,
                                     []>;
+    }
 }
 No newline at end of file

llvm/test/MC/Disassembler/PowerPC/ppc32-paired.txt

+# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-unknown -mcpu=750cl | FileCheck %s
+# CHECK: dcbz_l 0, 3
+0x10 0x00 0x1f 0xec
+# CHECK: psq_l 3, 4(13), 1, 0
+0xe0 0x6d 0x80 0x04
+# CHECK: psq_lu 3, 4(13), 1, 0
+0xe4 0x6d 0x80 0x04
+# CHECK: psq_lux 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x4c
+# CHECK: psq_lx 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x0c
+# CHECK: psq_st 3, 4(13), 1, 0
+0xf0 0x6d 0x80 0x04
+# CHECK: psq_stu 3, 4(13), 1, 0
+0xf4 0x6d 0x80 0x04
+# CHECK: psq_stux 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x4e
+# CHECK: psq_stx 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x0e
+# CHECK: ps_abs 3, 3
+0x10 0x60 0x1a 0x10
+# CHECK: ps_abs. 3, 3
+0x10 0x60 0x1a 0x11
+# CHECK: ps_add 3, 3, 4
+0x10 0x63 0x20 0x2a
+# CHECK: ps_add. 3, 3, 4
+0x10 0x63 0x20 0x2b
+# CHECK: ps_cmpo0 1, 3, 4
+0x10 0x83 0x20 0x40
+# CHECK: ps_cmpo1 1, 3, 4
+0x10 0x83 0x20 0xC0
+# CHECK: ps_cmpu0 1, 3, 4
+0x10 0x83 0x20 0x00
+# CHECK: ps_cmpu1 1, 3, 4
+0x10 0x83 0x20 0x80
+# CHECK: ps_div 3, 3, 4
+0x10 0x63 0x20 0x24
+# CHECK: ps_div. 3, 3, 4
+0x10 0x63 0x20 0x25
+# CHECK: ps_madd 3, 3, 4, 5
+0x10 0x63 0x29 0x3a
+# CHECK: ps_madd. 3, 3, 4, 5
+0x10 0x63 0x29 0x3b
+# CHECK: ps_madds0 3, 3, 4, 5
+0x10 0x63 0x29 0x1c
+# CHECK: ps_madds0. 3, 3, 4, 5
+0x10 0x63 0x29 0x1d
+# CHECK: ps_madds1 3, 3, 4, 5
+0x10 0x63 0x29 0x1e
+# CHECK: ps_madds1. 3, 3, 4, 5
+0x10 0x63 0x29 0x1f
+# CHECK: ps_merge00 3, 3, 4
+0x10 0x63 0x24 0x20
+# CHECK: ps_merge00. 3, 3, 4
+0x10 0x63 0x24 0x21
+# CHECK: ps_merge01 3, 3, 4
+0x10 0x63 0x24 0x60
+# CHECK: ps_merge01. 3, 3, 4
+0x10 0x63 0x24 0x61
+# CHECK: ps_merge10 3, 3, 4
+0x10 0x63 0x24 0xA0
+# CHECK: ps_merge10. 3, 3, 4
+0x10 0x63 0x24 0xA1
+# CHECK: ps_merge11 3, 3, 4
+0x10 0x63 0x24 0xE0
+# CHECK: ps_merge11. 3, 3, 4
+0x10 0x63 0x24 0xE1
+# CHECK: ps_mr 3, 4
+0x10 0x60 0x20 0x90
+# CHECK: ps_mr. 3, 4
+0x10 0x60 0x20 0x91
+# CHECK: ps_msub 3, 3, 4, 5
+0x10 0x63 0x29 0x38
+# CHECK: ps_msub. 3, 3, 4, 5
+0x10 0x63 0x29 0x39
+# CHECK: ps_mul 3, 3, 4
+0x10 0x63 0x01 0x32
+# CHECK: ps_mul. 3, 3, 4
+0x10 0x63 0x01 0x33
+# CHECK: ps_muls0 3, 3, 4
+0x10 0x63 0x01 0x18
+# CHECK: ps_muls0. 3, 3, 4
+0x10 0x63 0x01 0x19
+# CHECK: ps_muls1 3, 3, 4
+0x10 0x63 0x01 0x1A
+# CHECK: ps_muls1. 3, 3, 4
+0x10 0x63 0x01 0x1B
+# CHECK: ps_nabs 3, 3
+0x10 0x60 0x19 0x10
+# CHECK: ps_nabs. 3, 3
+0x10 0x60 0x19 0x11
+# CHECK: ps_neg 3, 3
+0x10 0x60 0x18 0x50
+# CHECK: ps_neg. 3, 3
+0x10 0x60 0x18 0x51
+# CHECK: ps_nmadd 3, 3, 4, 5
+0x10 0x63 0x29 0x3e
+# CHECK: ps_nmadd. 3, 3, 4, 5
+0x10 0x63 0x29 0x3f
+# CHECK: ps_nmsub 3, 3, 4, 5
+0x10 0x63 0x29 0x3c
+# CHECK: ps_nmsub. 3, 3, 4, 5
+0x10 0x63 0x29 0x3d
+# CHECK: ps_res 3, 3
+0x10 0x60 0x18 0x30
+# CHECK: ps_res. 3, 3
+0x10 0x60 0x18 0x31
+# CHECK: ps_rsqrte 3, 3
+0x10 0x60 0x18 0x34
+# CHECK: ps_rsqrte. 3, 3
+0x10 0x60 0x18 0x35
+# CHECK: ps_sel 3, 3, 4, 5
+0x10 0x63 0x29 0x2e
+# CHECK: ps_sel. 3, 3, 4, 5
+0x10 0x63 0x29 0x2f
+# CHECK: ps_sub 3, 3, 4
+0x10 0x63 0x20 0x28
+# CHECK: ps_sub. 3, 3, 4
+0x10 0x63 0x20 0x29
+# CHECK: ps_sum0 3, 3, 4, 5
+0x10 0x63 0x29 0x14
+# CHECK: ps_sum0. 3, 3, 4, 5
+0x10 0x63 0x29 0x15
+# CHECK: ps_sum1 3, 3, 4, 5
+0x10 0x63 0x29 0x16
+# CHECK: ps_sum1. 3, 3, 4, 5
+0x10 0x63 0x29 0x17
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