[PowerPC] Add Support for PPC750 Paired Single ext

[DarkKirb]

Summary

The Paired Single extension is a extension to the PowerPC ISA and is
found on the PPC 750CL-series processors. These processors were most
notably used in Nintendo home consoles.

The Paired Single extension adds a simple version of SIMD to the
architecture. Each SIMD Vector contains 2 32-bit floats. Most of the
floating-point instructions supported by the 750CL are also implemented
in the Paired Single extension.

This initial patch adds the following intrinsic declarations (in

alphabetic order):

v2f32 ppc_paired_l(const v2f32 *src, i1 word, i8 gqr);
void  ppc_paired_st(v2f32 val, v2f32 *dst, i1 word, i8 gqr);
v2f32 ppc_paired_madds0(v2f32 a, v2f32 b, v2f32 c);
v2f32 ppc_paired_madds1(v2f32 a, v2f32 b, v2f32 c);
v2f32 ppc_paired_merge00(v2f32 a, v2f32 b);
v2f32 ppc_paired_merge01(v2f32 a, v2f32 b);
v2f32 ppc_paired_merge10(v2f32 a, v2f32 b);
v2f32 ppc_paired_merge11(v2f32 a, v2f32 b);
v2f32 ppc_paired_muls0(v2f32 a, v2f32 b);
v2f32 ppc_paired_muls1(v2f32 a, v2f32 b);
v2f32 ppc_paired_sel(v2f32 sel, v2f32 a, v2f32 bit);
v2f32 ppc_paired_sum0(v2f32 a, v2f32 b, v2f32 c);
v2f32 ppc_paired_sum1(v2f32 a, v2f32 b, v2f32 c);

• ppc_paired_l maps to psq_l, psq_lx, psq_lu or psq_lux. It loads the paired single from the memory location
• ppc_paired_st maps to psq_st, psq_stx, psq_stu, or psq_stux. It stores the paired single to the memory location.
• ppc_paired_madds0 and ppc_paired_madds1 are multiply-accumulate a
  • c + b with the 1st or 2nd element of c being used for both elements respectively.
• ppc_paired_merge[01][01] merges the 1st/2nd element of the first vector with the 1st/2nd element of the second vector and creates a new vector
• ppc_paired_muls[01] multiply a with the 1st/2nd element of b (depending on the name)
• ppc_paired_sel is a dynamic variant of the merge* functions. It will take an element of vector a if the corresponding control entry is smaller than 0 and will use b otherwise
• ppc_paired_sum[01] will replace the 1st/2nd element of c with the sum of the first element of a and the second element of b

[PowerPC] Add Intrinsic for broadway-exclusive dcbz_l

A feature that only exists on the Nintendo Versions of the 750CL is the
locked cache. To support it one instruction was added: dcbz_l.

NOTE: this instruction is not the same as dcbzl. They have different instruction encodings and also different semantics. It works similar to dcbz, however it requires the locked cache to be enabled.

[PowerPC] Add assembly support for Paired Single

In particular, this commit adds support for the 32 2x32 bit "paired
single" point registers, makes changes to the calling convention to
support paired singles and adds all of the new instructions.

The ABI is not standardized everywhere. As far as I can tell there is no
standard ABI. Other compilers appear to not support passing paired
single types as arguments or to even interact with the extension at all
outside of inline assembly.

This calling convention is based on the Floating Point cc, meaning that
the first 8 arguments are stored in psf1-8 and 14-31 are callee-saved
registers. Another thing not found in the code is that GQR0 (SPR 912)
has to be set to 0. There is no GQR register class because the GQRs
can not be read or set from userspace.

Special thanks to Github user Tilka who created a similar, but much smaller patchset in 2014.

I'm currently working on getting codegen for the extension working. Many instructions are already working, however it is quite useless at the current stage since loads and stores are not working.

[DarkKirb]

This comment was removed by DarkKirb.

[DarkKirb]

This comment was removed by DarkKirb.

[DarkKirb]

[PowerPC] Add Test for Paired Single Decoding

This has uncovered multiple bugs with my previous implementation, namely that
ps_res and ps_frsqte had the wrong opcode and that the decoding for
immediate-offset loads and stores in ps_l* and ps_st* caused internal compiler
errors.

I couldn't reuse the logic from other immediate-offset code because

1. The register and the offset field are not right next to each other
2. The currently existing memri* asm operands are not 12 bit with unaligned offsets.

This commit also fixes the test suite for powerpc as it puts the new
instructions into a separate namespace (called Paired).

llvm/include/llvm/IR/IntrinsicsPowerPC.td

 
 def int_ppc_cfence : Intrinsic<[], [llvm_anyint_ty], []>;
 
 // PowerPC set FPSCR Intrinsic Definitions.
 def int_ppc_setrnd : GCCBuiltin<"__builtin_setrnd">,
       Intrinsic<[llvm_double_ty], [llvm_i32_ty], []>;
 
 }
+
+// Paired Single Intrinsics
+let TargetPrefix = "ppc" in {
+def int_ppc_paired_l: Intrinsic<[llvm_v2f32_ty], [llvm_ptr_ty, llvm_i1_ty, llvm_i8_ty], [IntrReadMem, IntrArgMemOnly, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
+def int_ppc_paired_st: Intrinsic<[], [llvm_v2f32_ty, llvm_ptr_ty, llvm_i1_ty, llvm_i8_ty], [IntrWriteMem, IntrArgMemOnly, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
+def int_ppc_paired_madds0: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_paired_madds1: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_paired_merge00: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty]>;
+def int_ppc_paired_merge01: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty]>;
+def int_ppc_paired_merge10: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty]>;
+def int_ppc_paired_merge11: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty]>;
+def int_ppc_paired_muls0: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_paired_muls1: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_paired_sel: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_paired_sum0: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_paired_sum1: Intrinsic<[llvm_v2f32_ty], [llvm_v2f32_ty, llvm_v2f32_ty, llvm_v2f32_ty], []>;
+def int_ppc_broadway_dcbz_l : Intrinsic<[], [llvm_ptr_ty], []>;
+}

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

bool isU7ImmX4() const { return Kind == Immediate &&
                                   (getImm() & 3) == 0; }
   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
   bool isU8ImmX8() const { return Kind == Immediate &&
                                   isUInt<8>(getImm()) &&
                                   (getImm() & 7) == 0; }
 
   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
+  bool isS12Imm() const {
+    return Kind == Expression || (Kind == Immediate && isInt<12>(getImm()));
+  }
   bool isU16Imm() const {
     switch (Kind) {
       case Expression:
         return true;
       case Immediate:
       case ContextImmediate:
         return isUInt<16>(getImmU16Context());
       default:
void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
   }
 
   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
   }
 
+  void addRegPSRCOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(PSRegs[getReg()]));
+  }
+
   void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
   }
 
   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

 }
 
 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, FRegs);
 }
 
+static DecodeStatus DecodePSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  return decodeRegisterClass(Inst, RegNo, PSRegs);
+}
+
 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VFRegs);
 }
 
 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 
   if (STI.getFeatureBits()[PPC::FeatureSPE]) {
     DecodeStatus result =
         decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
     if (result != MCDisassembler::Fail)
       return result;
   }
 
+  if (STI.getFeatureBits()[PPC::FeaturePaired]) {
+    DecodeStatus result = decodeInstruction(DecoderTablePairedSingle32, MI,
+                                            Inst, Address, this, STI);
+    if (result != MCDisassembler::Fail)
+      return result;
+  }
+
   return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
 }

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9,      \
         HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11,       \
         HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19,        \
         HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27,        \
         HI##28, HI##29, HI##30, HI##31                                         \
   }
 
 using llvm::MCPhysReg;
 
-#define DEFINE_PPC_REGCLASSES \
-  static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
-  static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
-  static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
-  static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
-  static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF); \
-  static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V); \
-  static const MCPhysReg RRegsNoR0[32] = \
-    PPC_REGS_NO0_31(PPC::ZERO, PPC::R); \
-  static const MCPhysReg XRegsNoX0[32] = \
-    PPC_REGS_NO0_31(PPC::ZERO8, PPC::X); \
-  static const MCPhysReg VSRegs[64] = \
-    PPC_REGS_LO_HI(PPC::VSL, PPC::V); \
-  static const MCPhysReg VSFRegs[64] = \
-    PPC_REGS_LO_HI(PPC::F, PPC::VF); \
-  static const MCPhysReg VSSRegs[64] = \
-    PPC_REGS_LO_HI(PPC::F, PPC::VF); \
-  static const MCPhysReg CRBITRegs[32] = { \
-    PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, \
-    PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
-    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
-    PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
-    PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
-    PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
-    PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
-    PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
-  static const MCPhysReg CRRegs[8] = { \
-    PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, \
+#define DEFINE_PPC_REGCLASSES                                                  \
+  static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R);                     \
+  static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X);                     \
+  static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F);                     \
+  static const MCPhysReg PSRegs[32] = PPC_REGS0_31(PPC::PSF);                  \
+  static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S);                   \
+  static const MCPhysReg VFRegs[32] = PPC_REGS0_31(PPC::VF);                   \
+  static const MCPhysReg VRegs[32] = PPC_REGS0_31(PPC::V);                     \
+  static const MCPhysReg RRegsNoR0[32] = PPC_REGS_NO0_31(PPC::ZERO, PPC::R);   \
+  static const MCPhysReg XRegsNoX0[32] = PPC_REGS_NO0_31(PPC::ZERO8, PPC::X);  \
+  static const MCPhysReg VSRegs[64] = PPC_REGS_LO_HI(PPC::VSL, PPC::V);        \
+  static const MCPhysReg VSFRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF);        \
+  static const MCPhysReg VSSRegs[64] = PPC_REGS_LO_HI(PPC::F, PPC::VF);        \
+  static const MCPhysReg CRBITRegs[32] = {                                     \
+      PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT, PPC::CR1GT,  \
+      PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,  \
+      PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT,  \
+      PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,  \
+      PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT,  \
+      PPC::CR7EQ, PPC::CR7UN};                                                 \
+  static const MCPhysReg CRRegs[8] = {PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,  \
                                       PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7}
 
 #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H

llvm/lib/Target/PowerPC/PPC.td

def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
                               "Enable floating-point instructions">;
 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
                               "Enable 64-bit registers usage for ppc32 [beta]">;
 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
                               "Use condition-register bits individually">;
 def FeatureFPU       : SubtargetFeature<"fpu","HasFPU","true",
                                         "Enable classic FPU instructions",
                                         [FeatureHardFloat]>;
+def FeaturePaired    : SubtargetFeature<"paired","HasPaired","true",
+                                        "Enable PPC750CL Paired-Single instructions",
+                                        [FeatureFPU]>;
 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
                                         "Enable Altivec instructions",
                                         [FeatureFPU]>;
 def FeatureSPE       : SubtargetFeature<"spe","HasSPE", "true",
                                         "Enable SPE instructions",
                                         [FeatureHardFloat]>;
 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
                                         "Enable the MFOCRF instruction">;
def : Processor<"604e", G3Itineraries, [Directive604,
                                         FeatureFRES, FeatureFRSQRTE,
                                         FeatureMFTB]>;
 def : Processor<"620", G3Itineraries, [Directive620,
                                        FeatureFRES, FeatureFRSQRTE,
                                        FeatureMFTB]>;
 def : Processor<"750", G4Itineraries, [Directive750,
                                        FeatureFRES, FeatureFRSQRTE,
                                        FeatureMFTB]>;
+def : Processor<"750cl", G3Itineraries, [Directive750,
+                                         FeatureFRES, FeatureFRSQRTE,
+                                         FeatureMFTB, FeaturePaired]>;
 def : Processor<"g3", G3Itineraries, [Directive750,
                                       FeatureFRES, FeatureFRSQRTE,
                                       FeatureMFTB]>;
 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
                                         FeatureFRES, FeatureFRSQRTE,
                                         FeatureMFTB]>;
 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
                                       FeatureFRES, FeatureFRSQRTE,

llvm/lib/Target/PowerPC/PPCCallingConv.td

def RetCC_PPC_Cold : CallingConv<[
   CCIfType<[i32], CCAssignToReg<[R3]>>,
   CCIfType<[i64], CCAssignToReg<[X3]>>,
   CCIfType<[i128], CCAssignToReg<[X3]>>,
 
   CCIfType<[f32], CCAssignToReg<[F1]>>,
   CCIfType<[f64], CCAssignToReg<[F1]>>,
   CCIfType<[f128], CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2]>>>,
 
+  CCIfType<[v2f32], CCIfSubtarget<"hasPaired()", CCAssignToReg<[PSF1]>>>,
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
            CCIfSubtarget<"hasAltivec()",
            CCAssignToReg<[V2]>>>
 ]>;
 
 // Return-value convention for PowerPC
 let Entry = 1 in
 def RetCC_PPC : CallingConv<[
def RetCC_PPC : CallingConv<[
   CCIfSubtarget<"hasSPE()",
        CCIfType<[f64], CCCustom<"CC_PPC32_SPE_RetF64">>>,
 
   // For P9, f128 are passed in vector registers.
   CCIfType<[f128],
            CCIfSubtarget<"hasP9Vector()",
            CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
 
+  CCIfType<[v2f32], CCIfSubtarget<"hasPaired()",
+           CCAssignToReg<[PSF1, PSF2, PSF3, PSF4, PSF5, PSF6, PSF7, PSF8]>>>,
   // Vector types returned as "direct" go into V2 .. V9; note that only the
   // ELFv2 ABI fully utilizes all these registers.
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
            CCIfSubtarget<"hasAltivec()",
-           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
+           CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
 ]>;
 
 // No explicit register is specified for the AnyReg calling convention. The
 // register allocator may assign the arguments to any free register.
 //
 // This calling convention is currently only supported by the stackmap and
 // patchpoint intrinsics. All other uses will result in an assert on Debug
 // builds. On Release builds we fallback to the PPC C calling convention.
def RetCC_PPC64_ELF_FIS : CallingConv<[
   CCIfType<[i32],  CCPromoteToType<i64>>,
   CCIfType<[i64],  CCAssignToReg<[X3, X4, X5, X6]>>,
   CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
   CCIfType<[f32],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
   CCIfType<[f64],  CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
   CCIfType<[f128],
            CCIfSubtarget<"hasP9Vector()",
            CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
+  CCIfType<[v2f32],
+           CCIfSubtarget<"hasPaired()",
+           CCAssignToReg<[PSF1, PSF2, PSF3, PSF4, PSF5, PSF6, PSF7, PSF8]>>>,
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
            CCIfSubtarget<"hasAltivec()",
            CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>
 ]>;
 
 //===----------------------------------------------------------------------===//
 // PowerPC System V Release 4 32-bit ABI
 //===----------------------------------------------------------------------===//

 def CC_PPC32_SVR4_VarArg : CallingConv<[
   CCDelegateTo<CC_PPC32_SVR4_Common>
 ]>;
 
 // In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
 // put vector arguments in vector registers before putting them on the stack.
 let Entry = 1 in
 def CC_PPC32_SVR4 : CallingConv<[
+  CCIfType<[v2f32], CCIfSubtarget<"hasPaired()",
+           CCAssignToReg<[PSF1, PSF2, PSF3, PSF4, PSF5, PSF6, PSF7, PSF8]>>>,
   // The first 12 Vector arguments are passed in AltiVec registers.
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
            CCIfSubtarget<"hasAltivec()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,
                           V8, V9, V10, V11, V12, V13]>>>,
 
   // Float128 types treated as vector arguments.
   CCIfType<[f128],
            CCIfSubtarget<"hasP9Vector()", CCAssignToReg<[V2, V3, V4, V5, V6, V7,

  
 let Entry = 1 in
 def CC_PPC32_SVR4_ByVal : CallingConv<[
   CCIfByVal<CCPassByVal<4, 4>>,
   
   CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
 ]>;
 
+def CSR_Paired : CalleeSavedRegs<(add PSF14, PSF15, PSF16, PSF17, PSF18, PSF19,
+                                  PSF20, PSF21, PSF22, PSF23, PSF24, PSF25,
+                                  PSF26, PSF27, PSF28, PSF29, PSF30, PSF31)>;
+
 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
                                        V28, V29, V30, V31)>;
 
 // SPE does not use FPRs, so break out the common register set as base.
 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
                                           R21, R22, R23, R24, R25, R26, R27,
                                           R28, R29, R30, R31, CR2, CR3, CR4
                                       )>;
 def CSR_SVR432 :  CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31
                                    )>;
 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
                                    S23, S24, S25, S26, S27, S28, S29, S30, S31
                               )>;
 
+def CSR_SVR432_Paired : CalleeSavedRegs<(add CSR_SVR432, CSR_Paired)>;
+
 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 
 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
 
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,
                                      F19, F20, F21, F22, F23, F24, F25, F26,

 // Do not include return registers r3, f1, v2.
 def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
                                                 (sequence "R%u", 14, 31),
                                                 (sequence "CR%u", 0, 7))>;
 
 def CSR_SVR32_ColdCC : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
                                           F0, (sequence "F%u", 2, 31))>;
 
+def CSR_SVR32_ColdCC_Paired : CalleeSavedRegs<(add CSR_SVR32_ColdCC,
+                                          PSF0, (sequence "PSF%u", 2, 31))>;
 
 def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC,
                                             (sequence "V%u", 0, 1),
                                             (sequence "V%u", 3, 31))>;
 
 def CSR_SVR32_ColdCC_SPE : CalleeSavedRegs<(add CSR_SVR32_ColdCC_Common,
                                             (sequence "S%u", 4, 10),
                                             (sequence "S%u", 14, 31))>;

llvm/lib/Target/PowerPC/PPCInstrFormats.td

class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
   let Inst{11-14} = 0;
   let Inst{15} = R;
   let Inst{16-20} = VRB;
   let Inst{21-22} = idx;
   let Inst{23-30} = xo;
   let Inst{31}    = RC;
 }
 
+// Paired-Single instruction formats
+class PSForm_xdab<bits<10> xo, dag OOL, dag IOL, string asmstr,
+                        InstrItinClass itin, list<dag> pattern>
+       : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> D;
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  bit RC = 0;
+
+  let Inst{6-10} = D;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31} = RC;
+}
+
+class PSForm_adabc<bits<5> xo, dag OOL, dag IOL, string asmstr,
+                        InstrItinClass itin, list<dag> pattern>
+       : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> D;
+  bits<5> A;
+  bits<5> B;
+  bits<5> C;
+
+  let Pattern = pattern;
+
+  bit RC = 0;
+
+  let Inst{6-10} = D;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-25} = C;
+  let Inst{26-30} = xo;
+  let Inst{31} = RC;
+}
+
+class PSQForm_xw<bits<6> op, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> D;
+  bits<5> A;
+  bits<5> B;
+  bit W;
+  bits<3> I;
+
+  let Pattern = pattern;
+
+  let Inst{6-10} = D;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21} = W;
+  let Inst{22-24} = I;
+  let Inst{25-30} = op;
+  let Inst{31} = 0; // no record mode supported
+}
+
+class PSQForm_dw<bits<6> op, dag OOL, dag IOL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+    :I<op, OOL, IOL, asmstr, itin> {
+  bits<5> D;
+  bit W;
+  bits<3> I;
+  bits<12> d;
+  bits<5> A;
+
+  let Pattern = pattern;
+
+  let Inst{6-10} = D;
+  let Inst{11-15} = A;
+  let Inst{16} = W;
+  let Inst{17-19} = I;
+  let Inst{20-31} = d;
+}
+
+class PSForm_xcrab<bit ordered, bit high, dag OOL, dag IOL, string asmstr,
+                   InstrItinClass itin, list<dag> pattern>
+  : I<4, OOL, IOL, asmstr, itin> {
+  bits<3> D;
+  bits<5> A;
+  bits<5> B;
+
+  let Inst{6-8} = D;
+  let Inst{9-10} = 0;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-23} = 0;
+  let Inst{24} = high;
+  let Inst{25} = ordered;
+  let Inst{26-31} = 0;
+}
+
+class PSForm_x0ab<bits<10> xo, dag OOL, dag IOL, string asmstr,
+                        InstrItinClass itin, list<dag> pattern>
+  : PSForm_xdab<xo, OOL, IOL, asmstr, itin, pattern> {
+  let D = 0;
+}
+
+class PSForm_xd0b<bits<10> xo, dag OOL, dag IOL, string asmstr,
+                        InstrItinClass itin, list<dag> pattern>
+  : PSForm_xdab<xo, OOL, IOL, asmstr, itin, pattern> {
+  let A = 0;
+}
+
+class PSForm_adab0<bits<5> xo, dag OOL, dag IOL, string asmstr,
+                   InstrItinClass itin, list<dag> pattern>
+  : PSForm_adabc<xo, OOL, IOL, asmstr, itin, pattern> {
+  let C = 0;
+}
+class PSForm_ada0c<bits<5> xo, dag OOL, dag IOL, string asmstr,
+                   InstrItinClass itin, list<dag> pattern>
+  : PSForm_adabc<xo, OOL, IOL, asmstr, itin, pattern> {
+  let B = 0;
+}
+class PSForm_ad0b0<bits<5> xo, dag OOL, dag IOL, string asmstr,
+                   InstrItinClass itin, list<dag> pattern>
+  : PSForm_adab0<xo, OOL, IOL, asmstr, itin, pattern> {
+  let A = 0;
+}
+
 //===----------------------------------------------------------------------===//
 // EmitTimePseudo won't have encoding information for the [MC]CodeEmitter
 // stuff
 class PPCEmitTimePseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
     : I<0, OOL, IOL, asmstr, NoItinerary> {
   let isCodeGenOnly = 1;
   let PPC64 = 0;
   let Pattern = pattern;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def f8rc : RegisterOperand<F8RC> {
   let ParserMatchClass = PPCRegF8RCAsmOperand;
 }
 def PPCRegF4RCAsmOperand : AsmOperandClass {
   let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
 }
 def f4rc : RegisterOperand<F4RC> {
   let ParserMatchClass = PPCRegF4RCAsmOperand;
 }
+def PPCRegPSRCAsmOperand : AsmOperandClass {
+  let Name = "RegPSRC"; let PredicateMethod = "isRegNumber";
+}
+def psrc : RegisterOperand<PSRC> {
+  let ParserMatchClass = PPCRegPSRCAsmOperand;
+}
 def PPCRegVRRCAsmOperand : AsmOperandClass {
   let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
 }
 def vrrc : RegisterOperand<VRRC> {
   let ParserMatchClass = PPCRegVRRCAsmOperand;
 }
 def PPCRegVFRCAsmOperand : AsmOperandClass {
   let Name = "RegVFRC"; let PredicateMethod = "isRegNumber";

 }
 def PPCDispSPE2Operand : AsmOperandClass {
  let Name = "DispSPE2"; let PredicateMethod = "isU6ImmX2";
  let RenderMethod = "addImmOperands";
 }
 def dispSPE2 : Operand<iPTR> {
   let ParserMatchClass = PPCDispSPE2Operand;
 }
+def PPCDispRID12Operand : AsmOperandClass {
+ let Name = "DispRID12"; let PredicateMethod = "isS12Imm";
+ let RenderMethod = "addImmOperands";
+}
+def dispRID12 : Operand<iPTR> {
+  let ParserMatchClass = PPCDispRID12Operand;
+}
 
 def memri : Operand<iPTR> {
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getMemRIEncoding";
   let DecoderMethod = "decodeMemRIOperands";
 }
 def memrr : Operand<iPTR> {
def spe4dis : Operand<iPTR> {   // SPE displacement where the imm is 4-aligned.
   let DecoderMethod = "decodeSPE4Operands";
 }
 def spe2dis : Operand<iPTR> {   // SPE displacement where the imm is 2-aligned.
   let PrintMethod = "printMemRegImm";
   let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg);
   let EncoderMethod = "getSPE2DisEncoding";
   let DecoderMethod = "decodeSPE2Operands";
 }
+def memrid12 : Operand<iPTR> { // Paired Single displacement where imm is 12 bits wide.
+  let PrintMethod = "printMemRegImm";
+  let MIOperandInfo = (ops dispRID12:$imm, ptr_rc_nor0:$reg);
+}
 
 // A single-register address. This is used with the SjLj
 // pseudo-instructions which translates to LD/LWZ.  These instructions requires
 // G8RC_NOX0 registers.
 def memr : Operand<iPTR> {
   let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg);
 }
 def PPCTLSRegOperand : AsmOperandClass {

 def IsBookE  : Predicate<"Subtarget->isBookE()">;
 def IsNotBookE  : Predicate<"!Subtarget->isBookE()">;
 def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
 def HasSYNC   : Predicate<"!Subtarget->hasOnlyMSYNC()">;
 def IsPPC4xx  : Predicate<"Subtarget->isPPC4xx()">;
 def IsPPC6xx  : Predicate<"Subtarget->isPPC6xx()">;
 def IsE500  : Predicate<"Subtarget->isE500()">;
 def HasSPE  : Predicate<"Subtarget->hasSPE()">;
+def HasPaired : Predicate<"Subtarget->hasPaired()">;
 def HasICBT : Predicate<"Subtarget->hasICBT()">;
 def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">;
 def NoNaNsFPMath
     : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
 def NaNsFPMath
     : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
 def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
 def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;

 
 // FCOPYSIGN's operand types need not agree.
 def : Pat<(fcopysign f64:$frB, f32:$frA),
           (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
 def : Pat<(fcopysign f32:$frB, f64:$frA),
           (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
 }
 
+include "PPCInstrPaired.td"
 include "PPCInstrAltivec.td"
 include "PPCInstrSPE.td"
 include "PPCInstr64Bit.td"
 include "PPCInstrVSX.td"
 include "PPCInstrHTM.td"
 
 def crnot : OutPatFrag<(ops node:$in),
                        (CRNOR $in, $in)>;

llvm/lib/Target/PowerPC/PPCInstrPaired.td

+//===-- PPCInstrPaired.td - The PowerPC Paired Single Extension -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the Paired Single extension to the PowerPC instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+multiclass PSForm_xdabr<bits<10> xo, dag OOL, dag IOL, string asmbase,
+                        string asmstr, InstrItinClass itin, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_xdab<xo, OOL, IOL,
+                           !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                           pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : PSForm_xdab<xo, OOL, IOL,
+                           !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                           []>, isRecordForm, RecFormRel;
+  }
+}
+
+multiclass PSForm_xd0br<bits<10> xo, dag OOL, dag IOL, string asmbase,
+                        string asmstr, InstrItinClass itin, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_xd0b<xo, OOL, IOL,
+                           !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                           pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : PSForm_xd0b<xo, OOL, IOL,
+                           !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                           []>, isRecordForm, RecFormRel;
+  }
+}
+
+multiclass PSForm_adabcr<bits<5> xo, dag OOL, dag IOL, string asmbase,
+                        string asmstr, InstrItinClass itin, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_adabc<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                            pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : PSForm_adabc<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                            []>, isRecordForm, RecFormRel;
+  }
+}
+
+multiclass PSForm_ada0cr<bits<5> xo, dag OOL, dag IOL, string asmbase,
+                        string asmstr, InstrItinClass itin, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_ada0c<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                            pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : PSForm_ada0c<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                            []>, isRecordForm, RecFormRel;
+  }
+}
+
+multiclass PSForm_adab0r<bits<5> xo, dag OOL, dag IOL, string asmbase,
+                        string asmstr, InstrItinClass itin, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_adab0<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                            pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : PSForm_adab0<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                            []>, isRecordForm, RecFormRel;
+  }
+}
+
+multiclass PSForm_ad0b0r<bits<5> xo, dag OOL, dag IOL, string asmbase,
+                        string asmstr, InstrItinClass itin, list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : PSForm_ad0b0<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                            pattern>, RecFormRel;
+    let Defs = [CR1] in
+    def _rec : PSForm_ad0b0<xo, OOL, IOL,
+                            !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                            []>, isRecordForm, RecFormRel;
+  }
+}
+
+let DecoderNamespace = "PairedSingle" in {
+    let Predicates = [HasPaired] in {
+        def DCBZ_L : PSForm_x0ab<1014, (outs), (ins memrr:$dst), "dcbz_l $dst",
+                                IIC_LdStDCBF, [(int_ppc_broadway_dcbz_l xoaddr:$dst)]>;
+
+        def PSQ_L : PSQForm_dw<56, (outs psrc:$fD), (ins memrid12:$src, u1imm:$W, u3imm:$I),
+                              "psq_l $fD, $src, $W, $I", IIC_LdStLoad, []>;
+
+        def PSQ_LU : PSQForm_dw<57, (outs psrc:$fD, ptr_rc_nor0:$ea_result),
+                                (ins memrid12:$src, u1imm:$W, u3imm:$I),
+                                "psq_lu $fD, $src, $W, $I", IIC_LdStLoadUpd, []>,
+                                RegConstraint<"$src.reg = $ea_result">,
+                                NoEncode<"$ea_result">;
+        def PSQ_LX : PSQForm_xw<6, (outs psrc:$fD), (ins memrr:$src, u1imm:$W, u3imm:$I),
+                                "psq_lx $fD, $src, $W, $I", IIC_LdStLoad, []>;
+        def PSQ_LUX : PSQForm_xw<38, (outs psrc:$fD, ptr_rc_nor0:$ea_result),
+                                (ins memrr:$src, u1imm:$W, u3imm:$I),
+                                "psq_lux $fD, $src, $W, $I", IIC_LdStLoad, []>,
+                                RegConstraint<"$src.ptrreg = $ea_result">,
+                                NoEncode<"$ea_result">;
+
+        def PSQ_ST : PSQForm_dw<60, (outs), (ins psrc:$fD, memrid12:$dst, u1imm:$W, u3imm:$I),
+                                "psq_st $fD, $dst, $W, $I", IIC_LdStStore, []>;
+
+        def PSQ_STU : PSQForm_dw<61, (outs ptr_rc_nor0:$ea_result),
+                                (ins psrc:$fD, memrid12:$dst, u1imm:$W, u3imm:$I),
+                                "psq_stu $fD, $dst, $W, $I", IIC_LdStSTU, []>,
+                                RegConstraint<"$dst.reg = $ea_result">,
+                                NoEncode<"$ea_result">;
+
+        def PSQ_STX : PSQForm_xw<7, (outs), (ins psrc:$fD, memrr:$dst, u1imm:$W, u3imm:$I),
+                                "psq_stx $fD, $dst, $W, $I", IIC_LdStStore, []>;
+
+        def PSQ_STUX : PSQForm_xw<39, (outs ptr_rc_nor0:$ea_result),
+                                  (ins psrc:$fD, memrr:$dst, u1imm:$W, u3imm:$I),
+                                  "psq_stux $fD, $dst, $W, $I", IIC_LdStSTUX, []>,
+                                  RegConstraint<"$dst.ptrreg = $ea_result">,
+                                  NoEncode<"$ea_result">;
+
+        defm PS_ABS : PSForm_xd0br<264, (outs psrc:$fD), (ins psrc:$fB),
+                                    "ps_abs", "$fD, $fB", IIC_FPGeneral,
+                                    [(set v2f32:$fD, (fabs v2f32:$fB))]>;
+
+        defm PS_ADD : PSForm_adab0r<21, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_add", "$fD, $fA, $fB", IIC_FPAddSub,
+                                    [(set v2f32:$fD, (fadd v2f32:$fA, v2f32:$fB))]>;
+
+        def PS_CMPU0 : PSForm_xcrab<0, 0, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_cmpu0 $crD, $fA, $fB", IIC_FPCompare, []>;
+        def PS_CMPU1 : PSForm_xcrab<0, 1, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_cmpu1 $crD, $fA, $fB", IIC_FPCompare, []>;
+        def PS_CMPO0 : PSForm_xcrab<1, 0, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_cmpo0 $crD, $fA, $fB", IIC_FPCompare, []>;
+        def PS_CMPO1 : PSForm_xcrab<1, 1, (outs crrc:$crD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_cmpo1 $crD, $fA, $fB", IIC_FPCompare, []>;
+
+        defm PS_DIV : PSForm_adab0r<18, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_div", "$fD, $fA, $fB", IIC_FPDivS,
+                                    [(set v2f32:$fD, (fdiv v2f32:$fA, v2f32:$fB))]>;
+
+        defm PS_MADD : PSForm_adabcr<29, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                    "ps_madd", "$fD, $fA, $fC, $fB", IIC_FPFused,
+                                    [(set v2f32:$fD, (fadd (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB))]>;
+
+        defm PS_MADDS0 : PSForm_adabcr<14, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                      "ps_madds0", "$fD, $fA, $fC, $fB", IIC_FPFused,
+                                      []>;
+
+        defm PS_MADDS1 : PSForm_adabcr<15, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                      "ps_madds1", "$fD, $fA, $fC, $fB", IIC_FPFused,
+                                      []>;
+        defm PS_MERGE00 : PSForm_xdabr<528, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                      "ps_merge00", "$fD, $fA, $fB", IIC_FPGeneral,
+                                      []>;
+        defm PS_MERGE01 : PSForm_xdabr<560, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                      "ps_merge01", "$fD, $fA, $fB", IIC_FPGeneral,
+                                      []>;
+        defm PS_MERGE10 : PSForm_xdabr<592, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                      "ps_merge10", "$fD, $fA, $fB", IIC_FPGeneral,
+                                      []>;
+        defm PS_MERGE11 : PSForm_xdabr<624, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                      "ps_merge11", "$fD, $fA, $fB", IIC_FPGeneral,
+                                      []>;
+        defm PS_MR : PSForm_xd0br<72, (outs psrc:$fD), (ins psrc:$fB),
+                                      "ps_mr", "$fD, $fB", IIC_FPGeneral,
+                                      [(set v2f32:$fD, v2f32:$fB)]>;
+
+        defm PS_MSUB : PSForm_adabcr<28, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                    "ps_msub", "$fD, $fA, $fC, $fB", IIC_FPFused,
+                                    [(set v2f32:$fD, (fsub (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB))]>;
+
+        defm PS_MUL : PSForm_ada0cr<25, (outs psrc:$fD), (ins psrc:$fA, psrc:$fC),
+                                    "ps_mul", "$fD, $fA, $fC", IIC_FPFused,
+                                    [(set v2f32:$fD, (fmul v2f32:$fA, v2f32:$fC))]>;
+
+        defm PS_MULS0 : PSForm_ada0cr<12, (outs psrc:$fD), (ins psrc:$fA, psrc:$fC),
+                                    "ps_muls0", "$fD, $fA, $fC", IIC_FPFused, []>;
+        defm PS_MULS1 : PSForm_ada0cr<13, (outs psrc:$fD), (ins psrc:$fA, psrc:$fC),
+                                    "ps_muls1", "$fD, $fA, $fC", IIC_FPFused, []>;
+
+        defm PS_NABS : PSForm_xd0br<136, (outs psrc:$fD), (ins psrc:$fB),
+                                    "ps_nabs", "$fD, $fB", IIC_FPGeneral,
+                                    [(set v2f32:$fD, (fneg (fabs v2f32:$fB)))]>;
+
+        defm PS_NEG : PSForm_xd0br<40, (outs psrc:$fD), (ins psrc:$fB),
+                                    "ps_neg", "$fD, $fB", IIC_FPGeneral,
+                                    [(set v2f32:$fD, (fneg v2f32:$fB))]>;
+
+        defm PS_NMADD : PSForm_adabcr<31, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                    "ps_nmadd", "$fD, $fA, $fC, $fB", IIC_FPFused,
+                                    [(set v2f32:$fD, (fneg (fadd (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB)))]>;
+
+       defm PS_NMSUB : PSForm_adabcr<30, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                    "ps_nmsub", "$fD, $fA, $fC, $fB", IIC_FPFused,
+                                    [(set v2f32:$fD, (fneg (fsub (fmul v2f32:$fA, v2f32:$fC), v2f32:$fB)))]>;
+
+        defm PS_RES : PSForm_ad0b0r<24, (outs psrc:$fD), (ins psrc:$fB),
+                                    "ps_res", "$fD, $fB", IIC_FPGeneral,
+                                    [(set v2f32:$fD, (PPCfre v2f32:$fB))]>;
+
+        defm PS_RSQRTE : PSForm_ad0b0r<26, (outs psrc:$fD), (ins psrc:$fB),
+                                      "ps_rsqrte", "$fD, $fB", IIC_FPGeneral,
+                                      [(set v2f32:$fD, (PPCfrsqrte v2f32:$fB))]>;
+
+      defm PS_SEL : PSForm_adabcr<23, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                  "ps_sel", "$fD, $fA, $fC, $fB", IIC_FPGeneral,
+                                  []>;
+
+        defm PS_SUB : PSForm_adab0r<20, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB),
+                                    "ps_sub", "$fD, $fA, $fB", IIC_FPAddSub,
+                                    [(set v2f32:$fD, (fsub v2f32:$fA, v2f32:$fB))]>;
+
+       defm PS_SUM0 : PSForm_adabcr<10, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                    "ps_sum0", "$fD, $fA, $fC, $fB", IIC_FPAddSub,
+                                    []>;
+      defm PS_SUM1 : PSForm_adabcr<11, (outs psrc:$fD), (ins psrc:$fA, psrc:$fB, psrc:$fC),
+                                    "ps_sum1", "$fD, $fA, $fC, $fB", IIC_FPAddSub,
+                                    []>;
+    }
+}
 No newline at end of file

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

if (TM.isPPC64()) {
         return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
                       : CSR_SVR64_ColdCC_Altivec_SaveList;
       return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
                     : CSR_SVR64_ColdCC_SaveList;
     }
     // 32-bit targets.
     if (Subtarget.hasAltivec())
       return CSR_SVR32_ColdCC_Altivec_SaveList;
+    else if (Subtarget.hasPaired())
+      return CSR_SVR32_ColdCC_Paired_SaveList;
     else if (Subtarget.hasSPE())
       return CSR_SVR32_ColdCC_SPE_SaveList;
     return CSR_SVR32_ColdCC_SaveList;
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
     if (Subtarget.hasAltivec())
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
                     : CSR_PPC64_Altivec_SaveList;
     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
   if (Subtarget.isAIXABI())
     return CSR_AIX32_SaveList;
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
+  if (Subtarget.hasPaired())
+    return CSR_SVR432_Paired_SaveList;
   else if (Subtarget.hasSPE())
     return CSR_SVR432_SPE_SaveList;
   return CSR_SVR432_SaveList;
 }
 
 const uint32_t *
 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                       CallingConv::ID CC) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_RegMask;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_RegMask;
     return CSR_64_AllRegs_RegMask;
   }
 
   if (Subtarget.isAIXABI()) {
     assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
     return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
   }
 
   if (CC == CallingConv::Cold) {
-    return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
-                                                  : CSR_SVR64_ColdCC_RegMask)
-                        : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
-                                                  : (Subtarget.hasSPE()
-                                                  ? CSR_SVR32_ColdCC_SPE_RegMask
-                                                  : CSR_SVR32_ColdCC_RegMask));
+    return TM.isPPC64()
+               ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
+               : (Subtarget.hasAltivec()
+                      ? CSR_SVR32_ColdCC_Altivec_RegMask
+                      : (Subtarget.hasPaired()
+                             ? CSR_SVR32_ColdCC_Paired_RegMask
+                                    : CSR_SVR32_ColdCC_RegMask)));
   }
 
-  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
-                                                : CSR_PPC64_RegMask)
-                      : (Subtarget.hasAltivec()
-                             ? CSR_SVR432_Altivec_RegMask
-                             : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
-                                                   : CSR_SVR432_RegMask));
+  return TM.isPPC64()
+             ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
+                    : (Subtarget.hasPaired()
+                           ? CSR_SVR432_Paired_RegMask
+                                                 : CSR_SVR432_RegMask)));
 }
 
 const uint32_t*
 PPCRegisterInfo::getNoPreservedMask() const {
   return CSR_NoRegs_RegMask;
 }
 
 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
if (Subtarget.is32BitELFABI() && IsPositionIndependent)
     markSuperRegs(Reserved, PPC::R30);
 
   // Reserve Altivec registers when Altivec is unavailable.
   if (!Subtarget.hasAltivec())
     for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
          IE = PPC::VRRCRegClass.end(); I != IE; ++I)
       markSuperRegs(Reserved, *I);
 
+  // Reserve Paired Single registers when PS is unavailable.
+  if (!Subtarget.hasPaired())
+    for (TargetRegisterClass::iterator I = PPC::PSRCRegClass.begin(),
+                                       IE = PPC::PSRCRegClass.end();
+         I != IE; ++I)
+      markSuperRegs(Reserved, *I);
+
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
   const MachineFrameInfo &MFI = MF.getFrameInfo();

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

class SPR<bits<10> num, string n> : PPCReg<n> {
   let HWEncoding{9-0} = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
 class FPR<bits<5> num, string n> : PPCReg<n> {
   let HWEncoding{4-0} = num;
 }
 
+// PSF - One of the 32 2x32-bit paired single floating-point registers
+class PSF<bits<5> num, string n> : PPCReg<n> {
+  let HWEncoding{4-0} = num;
+}
 // VF - One of the 32 64-bit floating-point subregisters of the vector
 // registers (used by VSX).
 class VF<bits<5> num, string n> : PPCReg<n> {
   let HWEncoding{4-0} = num;
   let HWEncoding{5} = 1;
 }
 
 // VR - One of the 32 128-bit vector registers

 }
 
 // Floating-point registers
 foreach Index = 0-31 in {
   def F#Index : FPR<Index, "f"#Index>,
                 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
 }
 
+// Paired Single floating-point registers
+foreach Index = 0-31 in {
+  def PSF#Index : PSF<Index, "f"#Index>;
+}
+
 // 64-bit Floating-point subregisters of Altivec registers
 // Note: the register names are v0-v31 or vs32-vs63 depending on the use.
 //       Custom C++ code is used to produce the correct name and encoding.
 foreach Index = 0-31 in {
   def VF#Index : VF<Index, "v" #Index>,
                  DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
 }
 

 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
 // previous stack frame. By allocating non-volatiles in reverse order we make
 // sure that the Floating-point register save area is always as small as
 // possible because there aren't any unused spill slots.
 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
                                                 (sequence "F%u", 31, 14))>;
 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
 
+def PSRC : RegisterClass<"PPC", [v2f32], 64, (add (sequence "PSF%u", 0, 13),
+                                                  (sequence "PSF%u", 31, 14))>;
+
 def VRRC : RegisterClass<"PPC",
                          [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],
                          128,
                          (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
                              V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
                              V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
 
 // VSX register classes (the allocation order mirrors that of the corresponding

llvm/lib/Target/PowerPC/PPCScheduleP9.td

def P9Model : SchedMachineModel {
   // resolved and they can be issued. Each of four execution slices has an
   // 11-entry iop issue queue.
   let MicroOpBufferSize = 44;
 
   let CompleteModel = 1;
 
   // Do not support SPE (Signal Processing Engine), prefixed instructions on
   // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
-  // introduced in ISA 3.1.
+  // introduced in ISA 3.1, or the Paired Single extension.
   let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
-                             PCRelativeMemops, IsISA3_1];
+                             PCRelativeMemops, IsISA3_1, HasPaired];
 }
 
 let SchedModel = P9Model in {
 
   // ***************** Processor Resources *****************
 
   // Dispatcher slots:
   // x0, x1, x2, and x3 are the dedicated slice dispatch ports, where each

llvm/lib/Target/PowerPC/PPCSubtarget.h

protected:
 
   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
   bool HasMFOCRF;
   bool Has64BitSupport;
   bool Use64BitRegs;
   bool UseCRBits;
   bool HasHardFloat;
   bool IsPPC64;
+  bool HasPaired;
   bool HasAltivec;
   bool HasFPU;
   bool HasSPE;
   bool HasVSX;
   bool NeedsTwoConstNR;
   bool HasP8Vector;
   bool HasP8Altivec;
   bool HasP8Crypto;
public:
   bool hasFRES() const { return HasFRES; }
   bool hasFRSQRTE() const { return HasFRSQRTE; }
   bool hasFRSQRTES() const { return HasFRSQRTES; }
   bool hasRecipPrec() const { return HasRecipPrec; }
   bool hasSTFIWX() const { return HasSTFIWX; }
   bool hasLFIWAX() const { return HasLFIWAX; }
   bool hasFPRND() const { return HasFPRND; }
   bool hasFPCVT() const { return HasFPCVT; }
+  bool hasPaired() const { return HasPaired; }
   bool hasAltivec() const { return HasAltivec; }
   bool hasSPE() const { return HasSPE; }
   bool hasFPU() const { return HasFPU; }
   bool hasVSX() const { return HasVSX; }
   bool needsTwoConstNR() const { return NeedsTwoConstNR; }
   bool hasP8Vector() const { return HasP8Vector; }
   bool hasP8Altivec() const { return HasP8Altivec; }
   bool hasP8Crypto() const { return HasP8Crypto; }

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

 void PPCSubtarget::initializeEnvironment() {
   StackAlignment = Align(16);
   CPUDirective = PPC::DIR_NONE;
   HasMFOCRF = false;
   Has64BitSupport = false;
   Use64BitRegs = false;
   UseCRBits = false;
   HasHardFloat = false;
+  HasPaired = false;
   HasAltivec = false;
   HasSPE = false;
   HasFPU = false;
   HasVSX = false;
   NeedsTwoConstNR = false;
   HasP8Vector = false;
   HasP8Altivec = false;
   HasP8Crypto = false;
if ((TargetTriple.isOSFreeBSD() && TargetTriple.getOSMajorVersion() >= 13) ||
     SecurePlt = true;
 
   if (HasSPE && IsPPC64)
     report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
   if (HasSPE && (HasAltivec || HasVSX || HasFPU))
     report_fatal_error(
         "SPE and traditional floating point cannot both be enabled.\n", false);
 
+  if (HasPaired && IsPPC64)
+    report_fatal_error("Paired Single is only supported for 32-bit targets.\n", false);
+  if (HasPaired && HasAltivec)
+    report_fatal_error("Paired Single and Altivec cannot both be enabled.\n", false);
+
   // If not SPE, set standard FPU
   if (!HasSPE)
     HasFPU = true;
 
   StackAlignment = getPlatformStackAlignment();
 
   // Determine endianness.
   // FIXME: Part of the TargetMachine.

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

switch (ClassID) {
     case VRRC:        return "PPC::VRRC";
     case VSXRC:       return "PPC::VSXRC";
   }
 }
 
 unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) const {
   if (Vector) {
     if (ST->hasAltivec()) return 128;
+    if (ST->hasPaired())
+      return 64;
     return 0;
   }
 
   if (ST->isPPC64())
     return 64;
   return 32;
 
 }

llvm/test/MC/Disassembler/PowerPC/ppc32-paired.txt

+# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-unknown -mcpu=750cl | FileCheck %s
+# CHECK: dcbz_l 0, 3
+0x10 0x00 0x1f 0xec
+# CHECK: psq_l 3, 4(13), 1, 0
+0xe0 0x6d 0x80 0x04
+# CHECK: psq_lu 3, 4(13), 1, 0
+0xe4 0x6d 0x80 0x04
+# CHECK: psq_lux 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x4c
+# CHECK: psq_lx 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x0c
+# CHECK: psq_st 3, 4(13), 1, 0
+0xf0 0x6d 0x80 0x04
+# CHECK: psq_stu 3, 4(13), 1, 0
+0xf4 0x6d 0x80 0x04
+# CHECK: psq_stux 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x4e
+# CHECK: psq_stx 3, 0, 3, 1, 0
+0x10 0x60 0x1c 0x0e
+# CHECK: ps_abs 3, 3
+0x10 0x60 0x1a 0x10
+# CHECK: ps_abs. 3, 3
+0x10 0x60 0x1a 0x11
+# CHECK: ps_add 3, 3, 4
+0x10 0x63 0x20 0x2a
+# CHECK: ps_add. 3, 3, 4
+0x10 0x63 0x20 0x2b
+# CHECK: ps_cmpo0 1, 3, 4
+0x10 0x83 0x20 0x40
+# CHECK: ps_cmpo1 1, 3, 4
+0x10 0x83 0x20 0xC0
+# CHECK: ps_cmpu0 1, 3, 4
+0x10 0x83 0x20 0x00
+# CHECK: ps_cmpu1 1, 3, 4
+0x10 0x83 0x20 0x80
+# CHECK: ps_div 3, 3, 4
+0x10 0x63 0x20 0x24
+# CHECK: ps_div. 3, 3, 4
+0x10 0x63 0x20 0x25
+# CHECK: ps_madd 3, 3, 4, 5
+0x10 0x63 0x29 0x3a
+# CHECK: ps_madd. 3, 3, 4, 5
+0x10 0x63 0x29 0x3b
+# CHECK: ps_madds0 3, 3, 4, 5
+0x10 0x63 0x29 0x1c
+# CHECK: ps_madds0. 3, 3, 4, 5
+0x10 0x63 0x29 0x1d
+# CHECK: ps_madds1 3, 3, 4, 5
+0x10 0x63 0x29 0x1e
+# CHECK: ps_madds1. 3, 3, 4, 5
+0x10 0x63 0x29 0x1f
+# CHECK: ps_merge00 3, 3, 4
+0x10 0x63 0x24 0x20
+# CHECK: ps_merge00. 3, 3, 4
+0x10 0x63 0x24 0x21
+# CHECK: ps_merge01 3, 3, 4
+0x10 0x63 0x24 0x60
+# CHECK: ps_merge01. 3, 3, 4
+0x10 0x63 0x24 0x61
+# CHECK: ps_merge10 3, 3, 4
+0x10 0x63 0x24 0xA0
+# CHECK: ps_merge10. 3, 3, 4
+0x10 0x63 0x24 0xA1
+# CHECK: ps_merge11 3, 3, 4
+0x10 0x63 0x24 0xE0
+# CHECK: ps_merge11. 3, 3, 4
+0x10 0x63 0x24 0xE1
+# CHECK: ps_mr 3, 4
+0x10 0x60 0x20 0x90
+# CHECK: ps_mr. 3, 4
+0x10 0x60 0x20 0x91
+# CHECK: ps_msub 3, 3, 4, 5
+0x10 0x63 0x29 0x38
+# CHECK: ps_msub. 3, 3, 4, 5
+0x10 0x63 0x29 0x39
+# CHECK: ps_mul 3, 3, 4
+0x10 0x63 0x01 0x32
+# CHECK: ps_mul. 3, 3, 4
+0x10 0x63 0x01 0x33
+# CHECK: ps_muls0 3, 3, 4
+0x10 0x63 0x01 0x18
+# CHECK: ps_muls0. 3, 3, 4
+0x10 0x63 0x01 0x19
+# CHECK: ps_muls1 3, 3, 4
+0x10 0x63 0x01 0x1A
+# CHECK: ps_muls1. 3, 3, 4
+0x10 0x63 0x01 0x1B
+# CHECK: ps_nabs 3, 3
+0x10 0x60 0x19 0x10
+# CHECK: ps_nabs. 3, 3
+0x10 0x60 0x19 0x11
+# CHECK: ps_neg 3, 3
+0x10 0x60 0x18 0x50
+# CHECK: ps_neg. 3, 3
+0x10 0x60 0x18 0x51
+# CHECK: ps_nmadd 3, 3, 4, 5
+0x10 0x63 0x29 0x3e
+# CHECK: ps_nmadd. 3, 3, 4, 5
+0x10 0x63 0x29 0x3f
+# CHECK: ps_nmsub 3, 3, 4, 5
+0x10 0x63 0x29 0x3c
+# CHECK: ps_nmsub. 3, 3, 4, 5
+0x10 0x63 0x29 0x3d
+# CHECK: ps_res 3, 3
+0x10 0x60 0x18 0x30
+# CHECK: ps_res. 3, 3
+0x10 0x60 0x18 0x31
+# CHECK: ps_rsqrte 3, 3
+0x10 0x60 0x18 0x34
+# CHECK: ps_rsqrte. 3, 3
+0x10 0x60 0x18 0x35
+# CHECK: ps_sel 3, 3, 4, 5
+0x10 0x63 0x29 0x2e
+# CHECK: ps_sel. 3, 3, 4, 5
+0x10 0x63 0x29 0x2f
+# CHECK: ps_sub 3, 3, 4
+0x10 0x63 0x20 0x28
+# CHECK: ps_sub. 3, 3, 4
+0x10 0x63 0x20 0x29
+# CHECK: ps_sum0 3, 3, 4, 5
+0x10 0x63 0x29 0x14
+# CHECK: ps_sum0. 3, 3, 4, 5
+0x10 0x63 0x29 0x15
+# CHECK: ps_sum1 3, 3, 4, 5
+0x10 0x63 0x29 0x16
+# CHECK: ps_sum1. 3, 3, 4, 5
+0x10 0x63 0x29 0x17
 No newline at end of file