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[WebAssembly] Implement prototype v128.load{32,64}_zero instructions

Authored by tlively on Jul 28 2020, 8:27 PM.



Specified in, these
instructions load the first vector lane from memory and zero the other
lanes. Since these instructions are not officially part of the SIMD
proposal, they are only available on an opt-in basis via LLVM
intrinsics and clang builtin functions. If these instructions are
merged to the proposal, this implementation will change so that the
instructions will be generated from normal IR. At that point the
intrinsics and builtin functions would be removed.

This PR also changes the opcodes for the experimental f32x4.qfm{a,s}
instructions because their opcodes conflicted with those of the
v128.load{32,64}_zero instructions. The new opcodes were chosen to
match those used in V8.

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Event Timeline

tlively created this revision.Jul 28 2020, 8:27 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJul 28 2020, 8:27 PM
tlively requested review of this revision.Jul 28 2020, 8:27 PM

Since this changes opcodes, it needs to be landed in concert with the corresponding Binaryen change.

aheejin accepted this revision.Jul 30 2020, 1:50 AM
aheejin added inline comments.

Can memory accesses be speculatable? The below too

This revision is now accepted and ready to land.Jul 30 2020, 1:50 AM
tlively updated this revision to Diff 282017.Jul 30 2020, 12:40 PM
  • Remove IntrSpeculatable
tlively added inline comments.Jul 30 2020, 5:42 PM

Hmm, maybe not, and it's definitely move conservative for them not to be.

tlively updated this revision to Diff 282680.Aug 3 2020, 10:50 AM
  • Renumber i32x4.dot_i16x8_s to match V8 as well
This revision was landed with ongoing or failed builds.Aug 3 2020, 1:54 PM
This revision was automatically updated to reflect the committed changes.