[AArch64][GlobalISel] Look through constants when selection stores of 0

[paquette]

Summary

Very minor code size improvements (hits 8 times in Bullet at -O3), but still something.

Also very minor NFC change to make sure we only search for a 0 constant when selecting a store. Before, we'd do this for loads as well.

[aemerson]

LGTM.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

#endif
     // If we haven't folded anything into our addressing mode yet, try to fold
     // a frame index into the base+offset.
     if (!Offset && PtrMI->getOpcode() == TargetOpcode::G_FRAME_INDEX)
       I.getOperand(1).ChangeToFrameIndex(PtrMI->getOperand(1).getIndex());
 
     I.addOperand(MachineOperand::CreateImm(Offset));
 
     // If we're storing a 0, use WZR/XZR.
-    if (auto CVal = getConstantVRegVal(ValReg, MRI)) {
-      if (*CVal == 0 && Opcode == TargetOpcode::G_STORE) {
+    if (Opcode == TargetOpcode::G_STORE) {
+      auto CVal = getConstantVRegValWithLookThrough(
+          ValReg, MRI, /*LookThroughInstrs = */ true,
+          /*HandleFConstants = */ false);
+      if (CVal && CVal->Value == 0) {
         unsigned Opc = I.getOpcode();
-        switch(Opc) {
-          case AArch64::STRWui:
-          case AArch64::STRHHui:
-          case AArch64::STRBBui:
-            I.getOperand(0).setReg(AArch64::WZR);
-            break;
-          case AArch64::STRXui:
-            I.getOperand(0).setReg(AArch64::XZR);
-            break;
+        switch (Opc) {
         }
       }
     }
 
     if (IsZExtLoad) {
       // The zextload from a smaller type to i32 should be handled by the importer.
       if (MRI.getType(ValReg).getSizeInBits() != 64)
         return false;

llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
   define void @store_s64_gpr(i64* %addr) { ret void }
   define void @store_s32_gpr(i32* %addr) { ret void }
   define void @store_s16_gpr(i16* %addr) { ret void }
   define void @store_s8_gpr(i8* %addr) { ret void }
 
   define void @store_zero_s64_gpr(i64* %addr) { ret void }
   define void @store_zero_s32_gpr(i32* %addr) { ret void }
   define void @store_zero_s16(i32* %addr) { ret void }
   define void @store_zero_s8(i32* %addr) { ret void }
+  define void @store_zero_look_through_cst(i32* %addr) { ret void }
 
   define void @store_fi_s64_gpr() {
     %ptr0 = alloca i64
     ret void
   }
 
   define void @store_gep_128_s64_gpr(i64* %addr) { ret void }
   define void @store_gep_512_s32_gpr(i32* %addr) { ret void }
bb.0:
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
     ; CHECK: STRBBui $wzr, [[COPY]], 0 :: (store 1)
     %0:gpr(p0) = COPY $x0
     %1:gpr(s8) = G_CONSTANT i8 0
     G_STORE %1(s8), %0(p0) :: (store 1)
 ...
 
 ---
+name:            store_zero_look_through_cst
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0:
+    liveins: $x0
+    ; CHECK-LABEL: name: store_zero_look_through_cst
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
+    ; CHECK: STRXui $xzr, [[COPY]], 0 :: (store 8 into %ir.addr)
+    %0:gpr(p0) = COPY $x0
+    %1:gpr(s32) = G_CONSTANT i32 0
+    %2:gpr(s64) = G_ZEXT %1
+    G_STORE  %2, %0 :: (store 8 into %ir.addr)
+...
+
+---
 name:            store_fi_s64_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }