Add LLVM support for remaining integer divide and permute instructions from ISA 2.06

[nemanjai]

Summary

This is the back end portion of Review D8398. Similarly to the front end, the back end got flags for checking if the target implements ISA 2.06 and up (and whether it is a Power7 and up CPU), etc.

The integer divide instructions that were already implemented were changed slightly since both the record form and the non-record form were specified as "First" and "Cracked". However, Book IV states that the non-record forms are not cracked. So I have changed the multiclass to specify this.
Finally, the record form instructions are implemented only for [inline] assembly and no builtins were provided. This is consistent with GCC. As noted in the front end review, the -mpopcntd option has no effect on these (in contrast with GCC).

[wschmidt]

Hi Nemanja,

Just a few minor inline comments. Good-looking patch otherwise!

include/llvm/IR/IntrinsicsPowerPC.td

50

OK, this is a real nit, but -- perhaps add a blank line before bpermd since this one is not a divide-extend as the comment would seem to imply.

lib/Target/PowerPC/PPCInstr64Bit.td

630

As discussed offline, I am bothered that these are not marked first-in-group but the regular divides are. Please check with Pat Haugen on correctness.

Long term, it makes no sense to have a single set of flags like this for each instruction, since these characteristics can and do change from one implementation to the next. But that will be a different patch...

lib/Target/PowerPC/PPCInstrInfo.td

717

I'm a tiny bit not enthused about the name -- IsPwr7OrHigher, perhaps? Pwr7Up sounds like an energy drink. ;) If nobody else dislikes it, leave it as is, though.

lib/Target/PowerPC/README.txt

626

Nit: No hyphen in "haphazard."

[hfinkel]

lib/Target/PowerPC/PPCInstrInfo.td

717

So true ;) -- Yea, I don't like it either.

Just make a target feature, and name it after some characteristic instruction. HasDIVDE perhaps?

lib/Target/PowerPC/PPCSubtarget.cpp

148

No... target features in PPC.td please.

[nemanjai]

include/llvm/IR/IntrinsicsPowerPC.td

50

This makes sense. I should probably have picked up on this. I'll add a blank line (or consider whether this definition belongs in a different part of the file).

lib/Target/PowerPC/PPCInstr64Bit.td

630

Thanks for bringing this up Bill. As it turns out, ALL cracked instructions are first in the dispatch group. For now, I will add PPC970_DGroup_First here as well. In the future, we can revisit how to accomplish this in a way that is specific to the CPU.

lib/Target/PowerPC/PPCInstrInfo.td

717

I thought it was funny when I came up with the name :-). 7Up, but the Power version. I will change it.

lib/Target/PowerPC/PPCSubtarget.cpp

148

In response to this comment and the one about the predicate...

The brief history of this design decision is that target features have a limitation. Namely, the target is limited to 64 of them. Now I haven't come across any fundamental reason for this, it is just that tblgen does not handle any more. The reason it doesn't is that in the generated code, each feature is a uint64_t entity that is 1 left-shifted by n (where n is the feature's zero-based ordinal number). At my last check, we were at around 58 features. So I did this to avoid blowing past the 64 feature limit for things that can easily be encoded in the C++ portion.
If everyone agrees that target features are the way to go and we don't want to worry about defining too many of these features, I'll be happy to change it.

lib/Target/PowerPC/README.txt

626

Oops, sorry, I'll fix it.

[hfinkel]

lib/Target/PowerPC/PPCSubtarget.cpp

148

Don't worry about it. Other targets are also running up against this limit, and there is a patchset under review to increase it.

[nemanjai]

Addressed comments from the previous review. Please note the resolution I've implemented for the comments about features that control these instructions. I felt that picking a characteristic instruction is also somewhat misleading (this patch is mostly divide instructions, but the next one will have more completely unrelated ones). So what I did instead is implement a feature that will enable all the features of a full ISA 2.06 implementation with -mattr=+isa-206 (subject to change if you would prefer a different string). The plan then is to do the same for ISA 2.07 in a later patch and if everyone agrees with this one.

[wschmidt]

Hi Nemanja,

Sorry to be a pain, but I don't support FeatureISA206 / FeatureISA207. See inline comment. :/ Hal, your thoughts?

Bill

lib/Target/PowerPC/PPC.td

163 ↗

(On Diff #22351)

I don't care for the FeatureISA206 choice. It contradicts the existing design (there are plenty of features called out that are also in ISA 2.06, so why is this one special?), and is redundant with Power7FeatureList (if you have a Power7FeatureList, shouldn't it just be previous features + FeatureISA206 under this philosophy?).

I think you should go back to Hal's suggestion and provide relevant features that are grouped in a reasonable way. For this patch, that would be something like FeatureExtDiv and FeatureBitPerm. I don't think we have a need to disrupt the existing design.

[hfinkel]

lib/Target/PowerPC/PPC.td

163 ↗

(On Diff #22351)

I agree with Bill agreeing with me ;)

That having been said, I would like to get a better handle on the features associated with ISA revisions, and group those together. So please add fine-grained features (for one thing, we'll likely have CodeGen support for these at some point, at least bpermd). As a separate change, we can add feature groups for the ISA revisions, and then use those to define the default sets of features for the processors defined.

[nemanjai]

lib/Target/PowerPC/PPC.td

163 ↗

(On Diff #22351)

OK, so to summarize:

• In this patch, add fine-grained control for the instructions that are implemented (I will add FeatureExtDiv and FeatureBitPerm - should I add a "d" at the end of that?)
• In a future patch, provide something along the lines of these feature groups (FeatureISA206 in this case)

[wschmidt]

lib/Target/PowerPC/PPC.td

163 ↗

(On Diff #22351)

You can add a "D" if you like; I don't care either way. It protects against a future feature that does bit permute on another data type, I suppose.

[hfinkel]

lib/Target/PowerPC/PPC.td

163 ↗

(On Diff #22351)

Yes, that sounds like a good plan. I think adding the D makes sense, I'd just name it, like others, based on the particular instruction: FeatureBPERMD since it refers to the particular instruction.

[nemanjai]

I've reverted back to using fine grained target features as requested in the last review. Since I am adding more Power7 features, I've condensed the feature list for pwr7 in a similar fashion to the way the feature list for pwr8 was done.

[wschmidt]

LGTM. Thanks for the revisions!

[nemanjai]

Committed revision 234546.

include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_sync : Intrinsic<[], [], []>;
   // lwsync is sync 1
   def int_ppc_lwsync : Intrinsic<[], [], []>;
 
   // Intrinsics used to generate ctr-based loops. These should only be
   // generated by the PowerPC backend!
   def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>;
   def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>;
+
+  // Intrinsics for [double]word extended forms of divide instructions
+  def int_ppc_divwe : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                                [IntrNoMem]>;
+  def int_ppc_divweu : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
+                                 [IntrNoMem]>;
+  def int_ppc_divde : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
+                                [IntrNoMem]>;
+  def int_ppc_divdeu : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
+                                 [IntrNoMem]>;
+  def int_ppc_bpermd : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
+                                 [IntrNoMem]>;
 }
 
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
   class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
                               list<LLVMType> param_types,
                               list<IntrinsicProperty> properties>

lib/Target/PowerPC/PPCInstr64Bit.td

defm SRADI  : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
                          "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
                          [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
                         "cntlzd", "$rA, $rS", IIC_IntGeneral,
                         [(set i64:$rA, (ctlz i64:$rS))]>;
 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
                        "popcntd $rA, $rS", IIC_IntGeneral,
                        [(set i64:$rA, (ctpop i64:$rS))]>;
+def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
+                     "bpermd $rA, $rS, $rB", IIC_IntGeneral,
+                     [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>,
+                     isPPC64, Requires<[IsPwr7Up]>;
 
 let isCodeGenOnly = 1, isCommutable = 1 in
 def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
                     "cmpb $rA, $rS, $rB", IIC_IntGeneral,
                     [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>;
 
 // popcntw also does a population count on the high 32 bits (storing the
 // results in the high 32-bits of the output). We'll ignore that here (which is
 // safe because we never separately use the high part of the 64-bit registers).
 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
                        "popcntw $rA, $rS", IIC_IntGeneral,
                        [(set i32:$rA, (ctpop i32:$rS))]>;
 
-defm DIVD  : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
+defm DIVD  : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                           "divd", "$rT, $rA, $rB", IIC_IntDivD,
-                       [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
-                       PPC970_DGroup_First, PPC970_DGroup_Cracked;
-defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
+                          [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64;
+defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                           "divdu", "$rT, $rA, $rB", IIC_IntDivD,
-                       [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
-                       PPC970_DGroup_First, PPC970_DGroup_Cracked;
+                          [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64;
+def DIVDE : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
+                     "divde $rT, $rA, $rB", IIC_IntDivD,
+                     [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>,
+                     isPPC64, Requires<[IsPwr7Up]>;
+let Defs = [CR0] in
+def DIVDEo : XOForm_1<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
+                      "divde. $rT, $rA, $rB", IIC_IntDivD,
+                      []>, isDOT, PPC970_DGroup_Cracked, isPPC64,
+                      Requires<[IsPwr7Up]>;
+def DIVDEU : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
+                      "divdeu $rT, $rA, $rB", IIC_IntDivD,
+                      [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>,
+                      isPPC64, Requires<[IsPwr7Up]>;
+let Defs = [CR0] in
+def DIVDEUo : XOForm_1<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
+                       "divdeu. $rT, $rA, $rB", IIC_IntDivD,
+                       []>, isDOT, PPC970_DGroup_Cracked, isPPC64,
+                       Requires<[IsPwr7Up]>;
 let isCommutable = 1 in
 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                        "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
                        [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
                        "mulli $rD, $rA, $imm", IIC_IntMulLI,
                        [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;

lib/Target/PowerPC/PPCInstrInfo.td

 def IsPPC4xx  : Predicate<"PPCSubTarget->isPPC4xx()">;
 def IsPPC6xx  : Predicate<"PPCSubTarget->isPPC6xx()">;
 def IsE500  : Predicate<"PPCSubTarget->isE500()">;
 def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
 def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
+def IsPwr7Up : Predicate<"PPCSubTarget->isPwr7Up()">;
+def IsPwr8Up : Predicate<"PPCSubTarget->isPwr8Up()">;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Multiclass Definitions.
 
 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
                        pattern>, RecFormRel;
     let Defs = [CR0] in
     def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
                        []>, isDOT, RecFormRel;
   }
 }
 
+// Multiclass for instructions for which the non record form is not cracked
+// and the record form is cracked (i.e. divw, mullw, etc.)
+multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
+                    string asmbase, string asmstr, InstrItinClass itin,
+                    list<dag> pattern> {
+  let BaseName = asmbase in {
+    def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
+                       !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
+                       pattern>, RecFormRel;
+    let Defs = [CR0] in
+    def o    : XOForm_1<opcode, xo, oe, OOL, IOL,
+                       !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
+                       []>, isDOT, RecFormRel, PPC970_DGroup_First,
+                       PPC970_DGroup_Cracked;
+  }
+}
+
 multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL,
                       string asmbase, string asmstr, InstrItinClass itin,
                       list<dag> pattern> {
   let BaseName = asmbase in {
     let Defs = [CARRY] in
     def NAME : XOForm_1<opcode, xo, oe, OOL, IOL,
                        !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
                        pattern>, RecFormRel;
def ADD4TLS  : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB),
                        "add $rT, $rA, $rB", IIC_IntSimple,
                        [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>;
 let isCommutable = 1 in
 defm ADDC  : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                         "addc", "$rT, $rA, $rB", IIC_IntGeneral,
                         [(set i32:$rT, (addc i32:$rA, i32:$rB))]>,
                         PPC970_DGroup_Cracked;
 
-defm DIVW  : XOForm_1r<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
+defm DIVW  : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                           "divw", "$rT, $rA, $rB", IIC_IntDivW,
-                       [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>,
-                       PPC970_DGroup_First, PPC970_DGroup_Cracked;
-defm DIVWU : XOForm_1r<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
+                          [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>;
+defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                           "divwu", "$rT, $rA, $rB", IIC_IntDivW,
-                       [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>,
-                       PPC970_DGroup_First, PPC970_DGroup_Cracked;
+                          [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>;
+def DIVWE : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
+                     "divwe $rT, $rA, $rB", IIC_IntDivW,
+                     [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>,
+                     Requires<[IsPwr7Up]>;
+let Defs = [CR0] in
+def DIVWEo : XOForm_1<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
+                      "divwe. $rT, $rA, $rB", IIC_IntDivW,
+                      []>, isDOT, PPC970_DGroup_Cracked, Requires<[IsPwr7Up]>;
+def DIVWEU : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
+                      "divweu $rT, $rA, $rB", IIC_IntDivW,
+                      [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>,
+                      Requires<[IsPwr7Up]>;
+let Defs = [CR0] in
+def DIVWEUo : XOForm_1<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
+                       "divweu. $rT, $rA, $rB", IIC_IntDivW,
+                       []>, isDOT, PPC970_DGroup_Cracked, Requires<[IsPwr7Up]>;
 let isCommutable = 1 in {
 defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                        "mulhw", "$rT, $rA, $rB", IIC_IntMulHW,
                        [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>;
 defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),
                        "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU,
                        [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>;
 defm MULLW : XOForm_1r<31, 235, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB),

lib/Target/PowerPC/PPCSubtarget.h

protected:
   unsigned StackAlignment;
 
   /// Selected instruction itineraries (one entry per itinerary class.)
   InstrItineraryData InstrItins;
 
   /// Which cpu directive was used.
   unsigned DarwinDirective;
 
+  // Features to identify whether the Target implements the minimum
+  // ISA. It is unnecessary to have separate SubtargetFeatures in the
+  // target description file for these.
+  bool IsPwr7Up, IsPwr8Up, IsISA206Up, IsISA207Up;
+
   /// Used by the ISel to turn in optimizations for POWER4-derived architectures
   bool HasMFOCRF;
   bool Has64BitSupport;
   bool Use64BitRegs;
   bool UseCRBits;
   bool IsPPC64;
   bool HasAltivec;
   bool HasSPE;
public:
   bool isE500() const { return IsE500; }
   bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
   bool isDeprecatedDST() const { return DeprecatedDST; }
   bool hasICBT() const { return HasICBT; }
   bool hasInvariantFunctionDescriptors() const {
     return HasInvariantFunctionDescriptors;
   }
   bool hasPartwordAtomics() const { return HasPartwordAtomics; }
+  bool isISA206Up() const { return IsISA206Up; }
+  bool isISA207Up() const { return IsISA207Up; }
+  bool isPwr7Up() const { return IsPwr7Up; }
+  bool isPwr8Up() const { return IsPwr8Up; }
 
   bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
   unsigned getPlatformStackAlignment() const {
     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
       return 32;
 
     return 16;
   }

lib/Target/PowerPC/PPCSubtarget.cpp

PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
                            const std::string &FS, const PPCTargetMachine &TM)
     : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
       IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
               TargetTriple.getArch() == Triple::ppc64le),
       TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
       InstrInfo(*this), TLInfo(TM, *this), TSInfo(TM.getDataLayout()) {}
 
 void PPCSubtarget::initializeEnvironment() {
+  IsPwr7Up = false;
+  IsPwr8Up = false;
+  IsISA206Up = false;
+  IsISA207Up = false;
   StackAlignment = 16;
   DarwinDirective = PPC::DIR_NONE;
   HasMFOCRF = false;
   Has64BitSupport = false;
   Use64BitRegs = false;
   UseCRBits = false;
   HasAltivec = false;
   HasSPE = false;
#endif
   // we're compiling for a BG/Q system regardless of whether or not QPX
   // is enabled because external functions will assume this alignment.
   IsQPXStackUnaligned = QPXStackUnaligned;
   StackAlignment = getPlatformStackAlignment();
 
   // Determine endianness.
   // FIXME: Part of the TargetMachine.
   IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
+
+  IsPwr8Up = CPUName == "ppc64le" || CPUName == "pwr8";
+  IsPwr7Up = CPUName == "pwr7" || IsPwr8Up;
+  IsISA206Up = IsPwr7Up;
+  IsISA207Up = IsPwr8Up;
 }
 
 /// hasLazyResolverStub - Return true if accesses to the specified global have
 /// to go through a dyld lazy resolution stub.  This means that an extra load
 /// is required to get the address of the global.
 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
   // We never have stubs if HasLazyResolverStubs=false or if in static mode.
   if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)

lib/Target/PowerPC/README.txt

 broken AFAIK, although it's not a target I can exercise.
 The following demonstrates the problem:
 extern void bar(char *p);
 void foo() {
   char x[100000];
   bar(x);
   __asm__("" ::: "cr2");
 }
+
+//===-------------------------------------------------------------------------===
+Naming convention for instruction formats is very hap-hazard.
+We have agreed on a naming scheme as follows:
+
+<INST_form>{_<OP_type><OP_len>}+
+
+Where:
+INST_form is the instruction format (X-form, etc.)
+OP_type is the operand type - one of OPC (opcode), RD (register destination),
+                              RS (register source),
+                              RDp (destination register pair),
+                              RSp (source register pair), IM (immediate),
+                              XO (extended opcode)
+OP_len is the length of the operand in bits
+
+VSX register operands would be of length 6 (split across two fields),
+condition register fields of length 3.
+We would not need denote reserved fields in names of instruction formats.

test/CodeGen/PowerPC/div-e-32.ll

+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define signext i32 @test1() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divwe 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divwe(i32, i32) #1
+
+; Function Attrs: nounwind
+define signext i32 @test2() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divweu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divweu(i32, i32) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"}

test/CodeGen/PowerPC/div-e-all.ll

+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define signext i32 @test1() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divwe(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divwe 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divwe(i32, i32) #1
+
+; Function Attrs: nounwind
+define signext i32 @test2() #0 {
+entry:
+  %0 = call i32 @llvm.ppc.divweu(i32 32, i32 16)
+  ret i32 %0
+; CHECK: divweu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.divweu(i32, i32) #1
+
+; Function Attrs: nounwind
+define i64 @test3() #0 {
+entry:
+  %0 = call i64 @llvm.ppc.divde(i64 32, i64 16)
+  ret i64 %0
+; CHECK: divde 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.divde(i64, i64) #1
+
+; Function Attrs: nounwind
+define i64 @test4() #0 {
+entry:
+  %0 = call i64 @llvm.ppc.divdeu(i64 32, i64 16)
+  ret i64 %0
+; CHECK: divdeu 3, 4, 3
+}
+
+; Function Attrs: nounwind readnone
+declare i64 @llvm.ppc.divdeu(i64, i64) #1
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 3.7.0 (trunk 231831) (llvm/trunk 231828:231843M)"}

test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x7c 0x43 0x23 0xd7
 
 # CHECK: divwu 2, 3, 4                   
 0x7c 0x43 0x23 0x96
 
 # CHECK: divwu. 2, 3, 4                  
 0x7c 0x43 0x23 0x97
 
+# CHECK: divwe 2, 3, 4
+0x7c 0x43 0x23 0x56
+
+# CHECK: divwe. 2, 3, 4
+0x7c 0x43 0x23 0x57
+
+# CHECK: divweu 2, 3, 4
+0x7c 0x43 0x23 0x16
+
+# CHECK: divweu. 2, 3, 4
+0x7c 0x43 0x23 0x17
+
 # CHECK: mulld 2, 3, 4                   
 0x7c 0x43 0x21 0xd2
 
 # CHECK: mulld. 2, 3, 4                  
 0x7c 0x43 0x21 0xd3
 
 # CHECK: mulhd 2, 3, 4                   
 0x7c 0x43 0x20 0x92

 0x7c 0x43 0x23 0xd3
 
 # CHECK: divdu 2, 3, 4                   
 0x7c 0x43 0x23 0x92
 
 # CHECK: divdu. 2, 3, 4                  
 0x7c 0x43 0x23 0x93
 
+# CHECK: divde 2, 3, 4
+0x7c 0x43 0x23 0x52
+
+# CHECK: divde. 2, 3, 4
+0x7c 0x43 0x23 0x53
+
+# CHECK: divdeu 2, 3, 4
+0x7c 0x43 0x23 0x12
+
+# CHECK: divdeu. 2, 3, 4
+0x7c 0x43 0x23 0x13
+
 # CHECK: cmpdi 2, 3, 128                 
 0x2d 0x23 0x00 0x80
 
 # CHECK: cmpd 2, 3, 4                    
 0x7d 0x23 0x20 0x00
 
 # CHECK: cmpldi 2, 3, 128                
 0x29 0x23 0x00 0x80

 0x7c 0x62 0x00 0x74
 
 # CHECK: cntlzd. 2, 3                    
 0x7c 0x62 0x00 0x75
 
 # CHECK: popcntd 2, 3                    
 0x7c 0x62 0x03 0xf4
 
+# CHECK: bpermd 2, 3, 4
+0x7c 0x62 0x21 0xf8
+
 # CHECK: cmpb 7, 21, 4
 0x7e 0xa7 0x23 0xf8
 
 # CHECK: rlwinm 2, 3, 4, 5, 6            
 0x54 0x62 0x21 0x4c
 
 # CHECK: rlwinm. 2, 3, 4, 5, 6           
 0x54 0x62 0x21 0x4d

test/MC/PowerPC/ppc64-encoding.s

 # CHECK-BE: divwu 2, 3, 4                   # encoding: [0x7c,0x43,0x23,0x96]
 # CHECK-LE: divwu 2, 3, 4                   # encoding: [0x96,0x23,0x43,0x7c]
             divwu 2, 3, 4
 # CHECK-BE: divwu. 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x97]
 # CHECK-LE: divwu. 2, 3, 4                  # encoding: [0x97,0x23,0x43,0x7c]
             divwu. 2, 3, 4
 # FIXME:    divwuo 2, 3, 4
 # FIXME:    divwuo. 2, 3, 4
-# FIXME:    divwe 2, 3, 4
-# FIXME:    divwe. 2, 3, 4
+# CHECK-BE: divwe 2, 3, 4                   # encoding: [0x7c,0x43,0x23,0x56]
+# CHECK-LE: divwe 2, 3, 4                   # encoding: [0x56,0x23,0x43,0x7c]
+            divwe 2, 3, 4
+# CHECK-BE: divwe. 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x57]
+# CHECK-LE: divwe. 2, 3, 4                  # encoding: [0x57,0x23,0x43,0x7c]
+            divwe. 2, 3, 4
 # FIXME:    divweo 2, 3, 4
 # FIXME:    divweo. 2, 3, 4
-# FIXME:    divweu 2, 3, 4
-# FIXME:    divweu. 2, 3, 4
+# CHECK-BE: divweu 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x16]
+# CHECK-LE: divweu 2, 3, 4                  # encoding: [0x16,0x23,0x43,0x7c]
+            divweu 2, 3, 4
+# CHECK-BE: divweu. 2, 3, 4                 # encoding: [0x7c,0x43,0x23,0x17]
+# CHECK-LE: divweu. 2, 3, 4                 # encoding: [0x17,0x23,0x43,0x7c]
+            divweu. 2, 3, 4
 # FIXME:    divweuo 2, 3, 4
 # FIXME:    divweuo. 2, 3, 4
 
 # CHECK-BE: mulld 2, 3, 4                   # encoding: [0x7c,0x43,0x21,0xd2]
 # CHECK-LE: mulld 2, 3, 4                   # encoding: [0xd2,0x21,0x43,0x7c]
             mulld 2, 3, 4
 # CHECK-BE: mulld. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0xd3]
 # CHECK-LE: mulld. 2, 3, 4                  # encoding: [0xd3,0x21,0x43,0x7c]

 # CHECK-BE: divdu 2, 3, 4                   # encoding: [0x7c,0x43,0x23,0x92]
 # CHECK-LE: divdu 2, 3, 4                   # encoding: [0x92,0x23,0x43,0x7c]
             divdu 2, 3, 4
 # CHECK-BE: divdu. 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x93]
 # CHECK-LE: divdu. 2, 3, 4                  # encoding: [0x93,0x23,0x43,0x7c]
             divdu. 2, 3, 4
 # FIXME:    divduo 2, 3, 4
 # FIXME:    divduo. 2, 3, 4
-# FIXME:    divde 2, 3, 4
-# FIXME:    divde. 2, 3, 4
+# CHECK-BE: divde 2, 3, 4                   # encoding: [0x7c,0x43,0x23,0x52]
+# CHECK-LE: divde 2, 3, 4                   # encoding: [0x52,0x23,0x43,0x7c]
+            divde 2, 3, 4
+# CHECK-BE: divde. 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x53]
+# CHECK-LE: divde. 2, 3, 4                  # encoding: [0x53,0x23,0x43,0x7c]
+            divde. 2, 3, 4
 # FIXME:    divdeo 2, 3, 4
 # FIXME:    divdeo. 2, 3, 4
-# FIXME:    divdeu 2, 3, 4
-# FIXME:    divdeu. 2, 3, 4
+# CHECK-BE: divdeu 2, 3, 4                  # encoding: [0x7c,0x43,0x23,0x12]
+# CHECK-LE: divdeu 2, 3, 4                  # encoding: [0x12,0x23,0x43,0x7c]
+            divdeu 2, 3, 4
+# CHECK-BE: divdeu. 2, 3, 4                 # encoding: [0x7c,0x43,0x23,0x13]
+# CHECK-LE: divdeu. 2, 3, 4                 # encoding: [0x13,0x23,0x43,0x7c]
+            divdeu. 2, 3, 4
 # FIXME:    divdeuo 2, 3, 4
 # FIXME:    divdeuo. 2, 3, 4
 
 # Fixed-point compare instructions
 
 # CHECK-BE: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
 # CHECK-LE: cmpdi 2, 3, 128                 # encoding: [0x80,0x00,0x23,0x2d]
             cmpi 2, 1, 3, 128

 # CHECK-LE: cntlzd 2, 3                     # encoding: [0x74,0x00,0x62,0x7c]
             cntlzd 2, 3
 # CHECK-BE: cntlzd. 2, 3                    # encoding: [0x7c,0x62,0x00,0x75]
 # CHECK-LE: cntlzd. 2, 3                    # encoding: [0x75,0x00,0x62,0x7c]
             cntlzd. 2, 3
 # CHECK-BE: popcntd 2, 3                    # encoding: [0x7c,0x62,0x03,0xf4]
 # CHECK-LE: popcntd 2, 3                    # encoding: [0xf4,0x03,0x62,0x7c]
             popcntd 2, 3
-# FIXME:    bpermd 2, 3, 4
+# CHECK-BE: bpermd 2, 3, 4                  # encoding: [0x7c,0x62,0x21,0xf8]
+# CHECK-LE: bpermd 2, 3, 4                  # encoding: [0xf8,0x21,0x62,0x7c]
+            bpermd 2, 3, 4
 
 # Fixed-point rotate and shift instructions
 
 # CHECK-BE: rlwinm 2, 3, 4, 5, 6            # encoding: [0x54,0x62,0x21,0x4c]
 # CHECK-LE: rlwinm 2, 3, 4, 5, 6            # encoding: [0x4c,0x21,0x62,0x54]
             rlwinm 2, 3, 4, 5, 6
 # CHECK-BE: rlwinm. 2, 3, 4, 5, 6           # encoding: [0x54,0x62,0x21,0x4d]
 # CHECK-LE: rlwinm. 2, 3, 4, 5, 6           # encoding: [0x4d,0x21,0x62,0x54]