[SystemZ] Allow specifying integer registers as part of the address calculation

[anirudhp]

Summary

• Previously this patch https://reviews.llvm.org/rGe1de2773a534957305d7a559c6d88c4b5ac354e2) provided support for accepting integer registers in inline asm

i.e.

__asm("lhi %r0, 5") -> lhi %r0, 5
__asm("lhi 0, 5") -> lhi 0,5

• This patch aims to extend this support to instructions which compute addresses as well. (i.e instructions of type BDMem and BD[X|R|V|L]Mem)

[uweigand]

A couple of cosmetic changes inline, otherwise the LGTM. Thanks!

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

907

Good point, this should be const.

959

Parentheses around HasVectorIndex are not necessary.

[Kai]

LGTM.

[anirudhp]

• Addressing the clang-tidy warning, adding const to the auto var
• Removing unnecessary parenthesis in a ternary assignment

[anirudhp]

@uweigand if you are happy with the patch and have no other comments for me to address, would you mind committing this? (as I don't have commit access)

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

private:
   struct Register {
     RegisterGroup Group;
     unsigned Num;
     SMLoc StartLoc, EndLoc;
   };
 
   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
 
+  bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
+
   OperandMatchResultTy parseRegister(OperandVector &Operands,
                                      RegisterKind Kind);
 
   OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
 
-  bool parseAddress(bool &HaveReg1, Register &Reg1,
-                    bool &HaveReg2, Register &Reg2,
-                    const MCExpr *&Disp, const MCExpr *&Length);
+  bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
+                    Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
+                    bool HasLength = false, bool HasVectorIndex = false);
   bool parseAddressRegister(Register &Reg);
 
   bool ParseDirectiveInsn(SMLoc L);
 
   OperandMatchResultTy parseAddress(OperandVector &Operands,
                                     MemoryKind MemKind,
                                     RegisterKind RegKind);
 
bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
   Reg.EndLoc = Parser.getTok().getLoc();
   Parser.Lex();
   return false;
 }
 
 // Parse a register of kind Kind and add it to Operands.
 OperandMatchResultTy
 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
-  SMLoc StartLoc, EndLoc;
-  unsigned RegNum;
-
-  // Handle register names of the form %<prefix><number>.
-  if (Parser.getTok().is(AsmToken::Percent)) {
-    Register Reg;
-    if (parseRegister(Reg))
-      return MatchOperand_ParseFail;
-
-    // Verify that a register prefix appropriate for Kind was used.
-    bool PrefixMatch;
-    switch (Kind) {
-    case GR32Reg:
-    case GRH32Reg:
-    case GR64Reg:
-    case GR128Reg:
-      PrefixMatch = Reg.Group == RegGR;
-      break;
-    case FP32Reg:
-    case FP64Reg:
-    case FP128Reg:
-      PrefixMatch = Reg.Group == RegFP;
-      break;
-    case VR32Reg:
-    case VR64Reg:
-    case VR128Reg:
-      // It is OK to use the %f prefix with vector instructions that
-      // expect some VR..Reg kind, so accept the RegFP group as well.
-      PrefixMatch = Reg.Group == RegV || Reg.Group == RegFP;
-      break;
-    case AR32Reg:
-      PrefixMatch = Reg.Group == RegAR;
-      break;
-    case CR64Reg:
-      PrefixMatch = Reg.Group == RegCR;
-      break;
-    }
-    if (!PrefixMatch) {
-      Error(Reg.StartLoc, "invalid operand for instruction");
-      return MatchOperand_ParseFail;
-    }
+  RegisterGroup Group;
+    Group = RegGR;
+    Group = RegFP;
+    Group = RegV;
+    Group = RegAR;
+    Group = RegCR;
 
-    RegNum = Reg.Num;
-    StartLoc = Reg.StartLoc;
-    EndLoc = Reg.EndLoc;
-  }
-  // Also allow specifying just a plain register number as integer.
-  else if (Parser.getTok().is(AsmToken::Integer)) {
-    const MCExpr *Register;
-    StartLoc = Parser.getTok().getLoc();
-    if (Parser.parseExpression(Register))
+  // Handle register names of the form %<prefix><number>
+  if (Parser.getTok().is(AsmToken::Percent)) {
+    if (parseRegister(Reg))
       return MatchOperand_ParseFail;
 
-    auto *CE = dyn_cast<MCConstantExpr>(Register);
-    if (!CE)
+    // Check the parsed register group "Reg.Group" with the expected "Group"
+    // Have to error out if user specified wrong prefix.
+    switch (Group) {
+    case RegGR:
+    case RegFP:
+    case RegAR:
+    case RegCR:
+      if (Group != Reg.Group) {
+        Error(Reg.StartLoc, "invalid operand for instruction");
         return MatchOperand_ParseFail;
-
-    int64_t MaxRegNum;
-    switch (Kind) {
-    case VR32Reg:
-    case VR64Reg:
-    case VR128Reg:
-      MaxRegNum = 31;
+      }
       break;
-    default:
-      MaxRegNum = 15;
+    case RegV:
+      if (Reg.Group != RegV && Reg.Group != RegFP) {
+        Error(Reg.StartLoc, "invalid operand for instruction");
+        return MatchOperand_ParseFail;
+      }
       break;
     }
-    int64_t Value = CE->getValue();
-    if (Value < 0 || Value > MaxRegNum) {
-      Error(StartLoc, "invalid register");
+  } else if (Parser.getTok().is(AsmToken::Integer)) {
+    if (parseIntegerRegister(Reg, Group))
       return MatchOperand_ParseFail;
-    }
-    RegNum = (unsigned) Value;
-
-    EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-  }
   // Otherwise we didn't match a register operand.
   else
     return MatchOperand_NoMatch;
 
   // Determine the LLVM register number according to Kind.
   const unsigned *Regs;
   switch (Kind) {
   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
   }
-  if (Regs[RegNum] == 0) {
-    Error(StartLoc, "invalid register pair");
+  if (Regs[Reg.Num] == 0) {
+    Error(Reg.StartLoc, "invalid register pair");
     return MatchOperand_ParseFail;
   }
 
-  Operands.push_back(SystemZOperand::createReg(Kind, Regs[RegNum],
-                                               StartLoc, EndLoc));
+  Operands.push_back(
+      SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
   return MatchOperand_Success;
 }
 
 // Parse any type of register (including integers) and add it to Operands.
 OperandMatchResultTy
 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
   // Handle integer values.
   if (Parser.getTok().is(AsmToken::Integer)) {
else {
     }
 
     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
                                                  Reg.StartLoc, Reg.EndLoc));
   }
   return MatchOperand_Success;
 }
 
+bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
+                                            RegisterGroup Group) {
+  Reg.StartLoc = Parser.getTok().getLoc();
+  // We have an integer token
+  const MCExpr *Register;
+  if (Parser.parseExpression(Register))
+    return true;
+
+  const auto *CE = dyn_cast<MCConstantExpr>(Register);
+  if (!CE)
+    return true;
+
+  int64_t MaxRegNum = (Group == RegV) ? 31 : 15;
+  int64_t Value = CE->getValue();
+  if (Value < 0 || Value > MaxRegNum) {
+    Error(Parser.getTok().getLoc(), "invalid register");
+    return true;
+  }
+
+  // Assign the Register Number
+  Reg.Num = (unsigned)Value;
+  Reg.Group = Group;
+  Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
+
+  // At this point, successfully parsed an integer register.
+  return false;
+}
+
 // Parse a memory operand into Reg1, Reg2, Disp, and Length.
 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
                                     bool &HaveReg2, Register &Reg2,
-                                    const MCExpr *&Disp,
-                                    const MCExpr *&Length) {
+                                    const MCExpr *&Disp, const MCExpr *&Length,
+                                    bool HasLength, bool HasVectorIndex) {
   // Parse the displacement, which must always be present.
   if (getParser().parseExpression(Disp))
     return true;
 
   // Parse the optional base and index.
   HaveReg1 = false;
   HaveReg2 = false;
   Length = nullptr;
+
+  // If we have a scenario as below:
+  //   vgef %v0, 0(0), 0
+  // This is an example of a "BDVMem" instruction type.
+  //
+  // So when we parse this as an integer register, the register group
+  // needs to be tied to "RegV". Usually when the prefix is passed in
+  // as %<prefix><reg-number> its easy to check which group it should belong to
+  // However, if we're passing in just the integer there's no real way to
+  // "check" what register group it should belong to.
+  //
+  // When the user passes in the register as an integer, the user assumes that
+  // the compiler is responsible for substituting it as the right kind of
+  // register. Whereas, when the user specifies a "prefix", the onus is on
+  // the user to make sure they pass in the right kind of register.
+  //
+  // The restriction only applies to the first Register (i.e. Reg1). Reg2 is
+  // always a general register. Reg1 should be of group RegV if "HasVectorIndex"
+  // (i.e. insn is of type BDVMem) is true.
+  RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR;
+
   if (getLexer().is(AsmToken::LParen)) {
     Parser.Lex();
 
     if (getLexer().is(AsmToken::Percent)) {
       // Parse the first register.
       HaveReg1 = true;
       if (parseRegister(Reg1))
         return true;
+    }
+    // So if we have an integer as the first token in ([tok1], ..), it could:
+    // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of
+    // instructions)
+    // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions)
+    else if (getLexer().is(AsmToken::Integer)) {
+      if (HasLength) {
+        // Instruction has a "Length" field, safe to parse the first token as
+        // the "Length" field
+        if (getParser().parseExpression(Length))
+          return true;
+      } else {
+        // Otherwise, if the instruction has no "Length" field, parse the
+        // token as a "Register". We don't have to worry about whether the
+        // instruction is invalid here, because the caller will take care of
+        // error reporting.
+        HaveReg1 = true;
+        if (parseIntegerRegister(Reg1, RegGroup))
+          return true;
+      }
     } else {
-      // Parse the length.
+      // If its not an integer or a percent token, then if the instruction
+      // is reported to have a "Length" then, parse it as "Length".
+      if (HasLength) {
         if (getParser().parseExpression(Length))
           return true;
       }
+    }
 
     // Check whether there's a second register.
     if (getLexer().is(AsmToken::Comma)) {
       Parser.Lex();
       HaveReg2 = true;
+
+      if (getLexer().is(AsmToken::Integer)) {
+        if (parseIntegerRegister(Reg2, RegGR))
+          return true;
+      } else {
         if (parseRegister(Reg2))
           return true;
       }
+    }
 
     // Consume the closing bracket.
     if (getLexer().isNot(AsmToken::RParen))
       return Error(Parser.getTok().getLoc(), "unexpected token in address");
     Parser.Lex();
   }
   return false;
 }

 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
                                RegisterKind RegKind) {
   SMLoc StartLoc = Parser.getTok().getLoc();
   unsigned Base = 0, Index = 0, LengthReg = 0;
   Register Reg1, Reg2;
   bool HaveReg1, HaveReg2;
   const MCExpr *Disp;
   const MCExpr *Length;
-  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length))
+
+  bool HasLength = (MemKind == BDLMem) ? true : false;
+  bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
+  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
+                   HasVectorIndex))
     return MatchOperand_ParseFail;
 
   const unsigned *Regs;
   switch (RegKind) {
   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
   default: llvm_unreachable("invalid RegKind");
   }
 
   switch (MemKind) {
   case BDMem:
     // If we have Reg1, it must be an address register.
     if (HaveReg1) {
       if (parseAddressRegister(Reg1))
         return MatchOperand_ParseFail;
       Base = Regs[Reg1.Num];
     }
-    // There must be no Reg2 or length.
-    if (Length) {
-      Error(StartLoc, "invalid use of length addressing");
-      return MatchOperand_ParseFail;
-    }
+    // There must be no Reg2.
     if (HaveReg2) {
       Error(StartLoc, "invalid use of indexed addressing");
       return MatchOperand_ParseFail;
     }
     break;
   case BDXMem:
     // If we have Reg1, it must be an address register.
     if (HaveReg1) {
       if (parseAddressRegister(Reg1))
         return MatchOperand_ParseFail;
       // If the are two registers, the first one is the index and the
       // second is the base.
       if (HaveReg2)
         Index = Regs[Reg1.Num];
       else
         Base = Regs[Reg1.Num];
     }
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
         return MatchOperand_ParseFail;
       Base = Regs[Reg2.Num];
     }
-    // There must be no length.
-    if (Length) {
-      Error(StartLoc, "invalid use of length addressing");
-      return MatchOperand_ParseFail;
-    }
     break;
   case BDLMem:
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
         return MatchOperand_ParseFail;
       Base = Regs[Reg2.Num];
     }
case BDRMem:
     }
     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
         return MatchOperand_ParseFail;
       Base = Regs[Reg2.Num];
     }
-    // There must be no length.
-    if (Length) {
-      Error(StartLoc, "invalid use of length addressing");
-      return MatchOperand_ParseFail;
-    }
     break;
   case BDVMem:
     // We must have Reg1, and it must be a vector register.
     if (!HaveReg1 || Reg1.Group != RegV) {
       Error(StartLoc, "vector index required in address");
       return MatchOperand_ParseFail;
     }
     Index = SystemZMC::VR128Regs[Reg1.Num];
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
         return MatchOperand_ParseFail;
       Base = Regs[Reg2.Num];
     }
-    // There must be no length.
-    if (Length) {
-      Error(StartLoc, "invalid use of length addressing");
-      return MatchOperand_ParseFail;
-    }
     break;
   }
 
   SMLoc EndLoc =
       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
                                                Index, Length, LengthReg,
                                                StartLoc, EndLoc));
   return MatchOperand_Success;
 }
 
 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
   StringRef IDVal = DirectiveID.getIdentifier();
bool SystemZAsmParser::parseOperand(OperandVector &Operands,
   // The only other type of operand is an immediate or address.  As above,
   // real address operands should have used a context-dependent parse routine,
   // so we treat any plain expression as an immediate.
   SMLoc StartLoc = Parser.getTok().getLoc();
   Register Reg1, Reg2;
   bool HaveReg1, HaveReg2;
   const MCExpr *Expr;
   const MCExpr *Length;
-  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length))
+  if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length,
+                   /*HasLength*/ true, /*HasVectorIndex*/ true))
     return true;
   // If the register combination is not valid for any instruction, reject it.
   // Otherwise, fall back to reporting an unrecognized instruction.
   if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV
       && parseAddressRegister(Reg1))
     return true;
   if (HaveReg2 && parseAddressRegister(Reg2))
     return true;

llvm/test/MC/SystemZ/insn-bad.s

#CHECK: cl  %r0, 4096
 
   cl  %r0, -1
   cl  %r0, 4096
 
 #CHECK: error: missing length in address
 #CHECK: clc 0, 0
 #CHECK: error: missing length in address
 #CHECK: clc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: clc 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: clc 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: clc 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: clc -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: ectg    0(%r1),4096(%r15), %r2
         ectg    4096(%r1),160(%r15), %r2
         ectg    0(%r1),-1(%r15), %r2
         ectg    0(%r1),4096(%r15), %r2
 
 #CHECK: error: missing length in address
 #CHECK: ed  0, 0
 #CHECK: error: missing length in address
 #CHECK: ed  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: ed  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: ed  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: ed  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: ed  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: ed  0(-), 0
   ed  0(%r1,%r2), 0(%r1)
   ed  0(1,%r2), 0(%r1,%r2)
   ed  0(-), 0
 
 #CHECK: error: missing length in address
 #CHECK: edmk  0, 0
 #CHECK: error: missing length in address
 #CHECK: edmk  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: edmk  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: edmk  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: edmk  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: edmk  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: msy %r0, 524288
 
   msy %r0, -524289
   msy %r0, 524288
 
 #CHECK: error: missing length in address
 #CHECK: mvc 0, 0
 #CHECK: error: missing length in address
 #CHECK: mvc 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvc 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: mvc 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvc 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvc -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: mvcdk 0(%r1),4096(%r15)
         mvcdk 4096(%r1),160(%r15)
         mvcdk 0(%r1),-1(%r15)
         mvcdk 0(%r1),4096(%r15)
 
 #CHECK: error: missing length in address
 #CHECK: mvcin 0, 0
 #CHECK: error: missing length in address
 #CHECK: mvcin 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvcin 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: mvcin 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvcin 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvcin -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: mvcin 0(-), 0
   mvcin  -1(1,%r1), 0(%r1)
   mvcin  4096(1,%r1), 0(%r1)
   mvcin  0(1,%r1), -1(%r1)
   mvcin  0(1,%r1), 4096(%r1)
   mvcin  0(%r1,%r2), 0(%r1)
   mvcin  0(1,%r2), 0(%r1,%r2)
   mvcin 0(-), 0
 
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvck  0(%r1,%r1), 0(2,%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvck  -1(%r1,%r1), 0(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvck  4096(%r1,%r1), 0(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvck  0(%r1,%r1), -1(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvck  0(%r1,%r1), 4096(%r1), %r3
 #CHECK: error: invalid use of indexed addressing
 #CHECK: mvck  0(%r1,%r2), 0(%r1,%r2), %r3
-#CHECK: error: unknown token in expression
+#CHECK: error: unexpected token in address
 #CHECK: mvck  0(-), 0, %r3
 
   mvck  0(%r1,%r1), 0(2,%r1), %r3
   mvck  -1(%r1,%r1), 0(%r1), %r3
   mvck  4096(%r1,%r1), 0(%r1), %r3
   mvck  0(%r1,%r1), -1(%r1), %r3
   mvck  0(%r1,%r1), 4096(%r1), %r3
   mvck  0(%r1,%r2), 0(%r1,%r2), %r3

 #CHECK: mvcos 0(%r1), 4096(%r15), %r2
 
         mvcos  160(%r1,%r15), 160(%r15), %r2
         mvcos  -1(%r1), 160(%r15), %r2
         mvcos  4096(%r1), 160(%r15), %r2
         mvcos  0(%r1), -1(%r15), %r2
         mvcos  0(%r1), 4096(%r15), %r2
 
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvcp  0(%r1,%r1), 0(2,%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcp  -1(%r1,%r1), 0(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcp  4096(%r1,%r1), 0(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcp  0(%r1,%r1), -1(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcp  0(%r1,%r1), 4096(%r1), %r3
 #CHECK: error: invalid use of indexed addressing
 #CHECK: mvcp  0(%r1,%r2), 0(%r1,%r2), %r3
-#CHECK: error: unknown token in expression
+#CHECK: error: unexpected token in address
 #CHECK: mvcp  0(-), 0, %r3
 
   mvcp  0(%r1,%r1), 0(2,%r1), %r3
   mvcp  -1(%r1,%r1), 0(%r1), %r3
   mvcp  4096(%r1,%r1), 0(%r1), %r3
   mvcp  0(%r1,%r1), -1(%r1), %r3
   mvcp  0(%r1,%r1), 4096(%r1), %r3
   mvcp  0(%r1,%r2), 0(%r1,%r2), %r3
   mvcp  0(-), 0, %r3
 
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvcs  0(%r1,%r1), 0(2,%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcs  -1(%r1,%r1), 0(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcs  4096(%r1,%r1), 0(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcs  0(%r1,%r1), -1(%r1), %r3
 #CHECK: error: invalid operand
 #CHECK: mvcs  0(%r1,%r1), 4096(%r1), %r3
 #CHECK: error: invalid use of indexed addressing
 #CHECK: mvcs  0(%r1,%r2), 0(%r1,%r2), %r3
-#CHECK: error: unknown token in expression
+#CHECK: error: unexpected token in address
 #CHECK: mvcs  0(-), 0, %r3
 
   mvcs  0(%r1,%r1), 0(2,%r1), %r3
   mvcs  -1(%r1,%r1), 0(%r1), %r3
   mvcs  4096(%r1,%r1), 0(%r1), %r3
   mvcs  0(%r1,%r1), -1(%r1), %r3
   mvcs  0(%r1,%r1), 4096(%r1), %r3
   mvcs  0(%r1,%r2), 0(%r1,%r2), %r3
#CHECK: mviy  0, 256
   mviy  0(%r1,%r2), 0
   mviy  0, -1
   mviy  0, 256
 
 #CHECK: error: missing length in address
 #CHECK: mvn 0, 0
 #CHECK: error: missing length in address
 #CHECK: mvn 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvn 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: mvn 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvn 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvn -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: mvo 0(-), 0(1)
   mvo  0(%r1,%r2), 0(1,%r1)
   mvo  0(1,%r2), 0(%r1,%r2)
   mvo 0(-), 0(1)
 
 #CHECK: error: missing length in address
 #CHECK: mvz 0, 0
 #CHECK: error: missing length in address
 #CHECK: mvz 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: mvz 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: mvz 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvz 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: mvz -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: n %r0, 4096
 
   n %r0, -1
   n %r0, 4096
 
 #CHECK: error: missing length in address
 #CHECK: nc  0, 0
 #CHECK: error: missing length in address
 #CHECK: nc  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: nc  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: nc  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: nc  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: nc  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: o %r0, 4096
 
   o %r0, -1
   o %r0, 4096
 
 #CHECK: error: missing length in address
 #CHECK: oc  0, 0
 #CHECK: error: missing length in address
 #CHECK: oc  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: oc  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: oc  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: oc  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: oc  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: pfdrl 1, 0x100000000
   pfdrl 1, -1
   pfdrl 1, 1
   pfdrl 1, 0x100000000
 
 #CHECK: error: missing length in address
 #CHECK: pka 0, 0
 #CHECK: error: missing length in address
 #CHECK: pka 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: pka 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: pka 0(%r1), 0(0,%r1)
 #CHECK: error: invalid operand
 #CHECK: pka 0(%r1), 0(257,%r1)
 #CHECK: error: invalid operand
 #CHECK: pka -1(%r1), 0(1,%r1)
 #CHECK: error: invalid operand
#CHECK: pka 0, 0(-)
   pka  0(%r1,%r2), 0(1,%r1)
   pka  0(%r2), 0(%r1,%r2)
   pka 0, 0(-)
 
 #CHECK: error: missing length in address
 #CHECK: pku 0, 0
 #CHECK: error: missing length in address
 #CHECK: pku 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: pku 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: pku 0(%r1), 0(0,%r1)
 #CHECK: error: invalid operand
 #CHECK: pku 0(%r1), 0(257,%r1)
 #CHECK: error: invalid operand
 #CHECK: pku -1(%r1), 0(1,%r1)
 #CHECK: error: invalid operand
#CHECK: srnmt 0(%r1,%r2)
   srnmt -1
   srnmt 4096
   srnmt 0(%r1,%r2)
 
 #CHECK: error: missing length in address
 #CHECK: srp 0, 0, 0
 #CHECK: error: missing length in address
 #CHECK: srp 0(%r1), 0(%r1), 0
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: srp 0(1,%r1), 0(2,%r1), 0
 #CHECK: error: invalid operand
 #CHECK: srp 0(0,%r1), 0(%r1), 0
 #CHECK: error: invalid operand
 #CHECK: srp 0(17,%r1), 0(%r1), 0
 #CHECK: error: invalid operand
 #CHECK: srp -1(1,%r1), 0(%r1), 0
 #CHECK: error: invalid operand
#CHECK: tprot   0(%r1),4096(%r15)
         tprot   4096(%r1),160(%r15)
         tprot   0(%r1),-1(%r15)
         tprot   0(%r1),4096(%r15)
 
 #CHECK: error: missing length in address
 #CHECK: tr  0, 0
 #CHECK: error: missing length in address
 #CHECK: tr  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: tr  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: tr  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: tr  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: tr  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: trot  %r2, %r4, 16
   trot  %r1, %r0
   trot  %r2, %r4, -1
   trot  %r2, %r4, 16
 
 #CHECK: error: missing length in address
 #CHECK: trt 0, 0
 #CHECK: error: missing length in address
 #CHECK: trt 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: trt 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: trt 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: trt 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: trt -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: trto  %r2, %r4, 16
   trto  %r1, %r0
   trto  %r2, %r4, -1
   trto  %r2, %r4, 16
 
 #CHECK: error: missing length in address
 #CHECK: trtr  0, 0
 #CHECK: error: missing length in address
 #CHECK: trtr  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: trtr  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: trtr  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: trtr  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: trtr  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: unpk  0(-), 0(1)
   unpk  0(%r1,%r2), 0(1,%r1)
   unpk  0(1,%r2), 0(%r1,%r2)
   unpk  0(-), 0(1)
 
 #CHECK: error: missing length in address
 #CHECK: unpka 0, 0
 #CHECK: error: missing length in address
 #CHECK: unpka 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: unpka 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: unpka 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: unpka 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: unpka -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: unpka 0(-), 0
   unpka  0(%r1,%r2), 0(%r1)
   unpka  0(1,%r2), 0(%r1,%r2)
   unpka 0(-), 0
 
 #CHECK: error: missing length in address
 #CHECK: unpku 0, 0
 #CHECK: error: missing length in address
 #CHECK: unpku 0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: unpku 0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: unpku 0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: unpku 0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: unpku -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand
#CHECK: x %r0, 4096
 
   x %r0, -1
   x %r0, 4096
 
 #CHECK: error: missing length in address
 #CHECK: xc  0, 0
 #CHECK: error: missing length in address
 #CHECK: xc  0(%r1), 0(%r1)
-#CHECK: error: invalid use of length addressing
+#CHECK: error: invalid use of indexed addressing
 #CHECK: xc  0(1,%r1), 0(2,%r1)
 #CHECK: error: invalid operand
 #CHECK: xc  0(0,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: xc  0(257,%r1), 0(%r1)
 #CHECK: error: invalid operand
 #CHECK: xc  -1(1,%r1), 0(%r1)
 #CHECK: error: invalid operand

llvm/test/MC/SystemZ/insn-good-z13.s

 #CHECK: vgef    %v0, 0(%v0,%r1), 3      # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
 #CHECK: vgef    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
 #CHECK: vgef    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
 #CHECK: vgef    %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x13]
 #CHECK: vgef    %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x13]
 #CHECK: vgef    %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x13]
 #CHECK: vgef    %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13]
 #CHECK: vgef    %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r1), 3      # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r1), 3      # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
+#CHECK: vgef    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x13]
+#CHECK: vgef    %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x13]
+#CHECK: vgef    %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x13]
+#CHECK: vgef    %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13]
+#CHECK: vgef    %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13]
 
   vgef  %v0, 0(%v0), 0
   vgef  %v0, 0(%v0,%r1), 0
   vgef  %v0, 0(%v0,%r1), 3
   vgef  %v0, 0(%v0,%r15), 0
   vgef  %v0, 0(%v15,%r1), 0
   vgef  %v0, 0(%v31,%r1), 0
   vgef  %v0, 4095(%v0, %r1), 0
   vgef  %v15, 0(%v0,%r1), 0
   vgef  %v31, 0(%v0,%r1), 0
   vgef  %v10, 1000(%v19,%r7), 1
+  vgef  %v0, 0(0,%r1), 0
+  vgef  %v0, 0(%v0,1), 3
+  vgef  %v0, 0(0,%r15), 0
+  vgef  %v0, 0(%v15,1), 0
+  vgef  0, 0(0), 0
+  vgef  0, 0(0,1), 0
+  vgef  0, 0(0,1), 3
+  vgef  0, 0(0,15), 0
+  vgef  0, 0(15,1), 0
+  vgef  0, 0(31,1), 0
+  vgef  0, 4095(0, 1), 0
+  vgef  15, 0(0,1), 0
+  vgef  31, 0(0,1), 0
+  vgef  10, 1000(19,7), 1
 
 #CHECK: vgeg    %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
 #CHECK: vgeg    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
 #CHECK: vgeg    %v0, 0(%v0,%r1), 1      # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
 #CHECK: vgeg    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
 #CHECK: vgeg    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
 #CHECK: vgeg    %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x12]
 #CHECK: vgeg    %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x12]
 #CHECK: vgeg    %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x12]
 #CHECK: vgeg    %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12]
 #CHECK: vgeg    %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r1), 1      # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v0), 0          # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r1), 0      # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r1), 1      # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
+#CHECK: vgeg    %v0, 0(%v0,%r15), 0     # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v0, 0(%v31,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x04,0x12]
+#CHECK: vgeg    %v0, 4095(%v0,%r1), 0   # encoding: [0xe7,0x00,0x1f,0xff,0x00,0x12]
+#CHECK: vgeg    %v15, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x00,0x12]
+#CHECK: vgeg    %v31, 0(%v0,%r1), 0     # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12]
+#CHECK: vgeg    %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12]
 
   vgeg  %v0, 0(%v0), 0
   vgeg  %v0, 0(%v0,%r1), 0
   vgeg  %v0, 0(%v0,%r1), 1
   vgeg  %v0, 0(%v0,%r15), 0
   vgeg  %v0, 0(%v15,%r1), 0
   vgeg  %v0, 0(%v31,%r1), 0
   vgeg  %v0, 4095(%v0,%r1), 0
   vgeg  %v15, 0(%v0,%r1), 0
   vgeg  %v31, 0(%v0,%r1), 0
   vgeg  %v10, 1000(%v19,%r7), 1
+  vgeg  %v0, 0(0,%r1), 0
+  vgeg  %v0, 0(%v0,1), 1
+  vgeg  %v0, 0(0,%r15), 0
+  vgeg  %v0, 0(%v15,1), 0
+  vgeg  0, 0(0), 0
+  vgeg  0, 0(0,1), 0
+  vgeg  0, 0(0,1), 1
+  vgeg  0, 0(0,15), 0
+  vgeg  0, 0(15,1), 0
+  vgeg  0, 0(31,1), 0
+  vgeg  0, 4095(0,1), 0
+  vgeg  15, 0(0,1), 0
+  vgeg  31, 0(0,1), 0
+  vgeg  10, 1000(19,7), 1
+
 
 #CHECK: vgfm    %v0, %v0, %v0, 0        # encoding: [0xe7,0x00,0x00,0x00,0x00,0xb4]
 #CHECK: vgfm    %v0, %v0, %v0, 15       # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xb4]
 #CHECK: vgfm    %v0, %v0, %v31, 0       # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xb4]
 #CHECK: vgfm    %v0, %v31, %v0, 0       # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xb4]
 #CHECK: vgfm    %v31, %v0, %v0, 0       # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xb4]
 #CHECK: vgfm    %v18, %v3, %v20, 11     # encoding: [0xe7,0x23,0x40,0x00,0xba,0xb4]
 

 #CHECK: vlbb    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07]
 #CHECK: vlbb    %v0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07]
 #CHECK: vlbb    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x07]
 #CHECK: vlbb    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x07]
 #CHECK: vlbb    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
 #CHECK: vlbb    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x07]
 #CHECK: vlbb    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x07]
 #CHECK: vlbb    %v18, 1383(%r3,%r4), 8  # encoding: [0xe7,0x23,0x45,0x67,0x88,0x07]
+#CHECK: vlbb    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
+#CHECK: vlbb    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
+#CHECK: vlbb    %v0, 0, 0               # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07]
+#CHECK: vlbb    %v0, 0, 15              # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07]
+#CHECK: vlbb    %v0, 4095, 0            # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x07]
+#CHECK: vlbb    %v0, 0(%r15), 0         # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x07]
+#CHECK: vlbb    %v0, 0(%r15,%r1), 0     # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x07]
+#CHECK: vlbb    %v15, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x07]
+#CHECK: vlbb    %v31, 0, 0              # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x07]
+#CHECK: vlbb    %v18, 1383(%r3,%r4), 8  # encoding: [0xe7,0x23,0x45,0x67,0x88,0x07]
 
   vlbb  %v0, 0, 0
   vlbb  %v0, 0, 15
   vlbb  %v0, 4095, 0
   vlbb  %v0, 0(%r15), 0
   vlbb  %v0, 0(%r15,%r1), 0
   vlbb  %v15, 0, 0
   vlbb  %v31, 0, 0
   vlbb  %v18, 1383(%r3,%r4), 8
+  vlbb  %v18, 1383(%r3, 4), 8
+  vlbb  %v0, 0(15,%r1), 0
+  vlbb  %v0, 0(%r15,1), 0
+  vlbb  0, 0, 0
+  vlbb  0, 0, 15
+  vlbb  0, 4095, 0
+  vlbb  0, 0(15), 0
+  vlbb  0, 0(15,1), 0
+  vlbb  15, 0, 0
+  vlbb  31, 0, 0
+  vlbb  18, 1383(3,4), 8
 
 #CHECK: vlc     %v0, %v0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x00,0xde]
 #CHECK: vlc     %v0, %v0, 15            # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xde]
 #CHECK: vlc     %v0, %v15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xde]
 #CHECK: vlc     %v0, %v31, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xde]
 #CHECK: vlc     %v15, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xde]
 #CHECK: vlc     %v31, %v0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xde]
 #CHECK: vlc     %v14, %v17, 11          # encoding: [0xe7,0xe1,0x00,0x00,0xb4,0xde]
#CHECK: vlvgb   %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x08,0x22]
   vlvgb %v0, %r15, 0
   vlvgb %v15, %r0, 0
   vlvgb %v31, %r0, 0
   vlvgb %v18, %r3, 1383(%r4)
 
 #CHECK: vlvgf   %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x20,0x22]
 #CHECK: vlvgf   %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x20,0x22]
 #CHECK: vlvgf   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x22]
+#CHECK: vlvgf   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x20,0x22]
 #CHECK: vlvgf   %v0, %r15, 0            # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x22]
 #CHECK: vlvgf   %v15, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x22]
 #CHECK: vlvgf   %v31, %r0, 0            # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x22]
 #CHECK: vlvgf   %v18, %r3, 1383(%r4)    # encoding: [0xe7,0x23,0x45,0x67,0x28,0x22]
 
   vlvgf %v0, %r0, 0
   vlvgf %v0, %r0, 4095
   vlvgf %v0, %r0, 0(%r15)
+  vlvgf %v0, %r0, 0(15)
   vlvgf %v0, %r15, 0
   vlvgf %v15, %r0, 0
   vlvgf %v31, %r0, 0
   vlvgf %v18, %r3, 1383(%r4)
 
 #CHECK: vlvgg   %v0, %r0, 0             # encoding: [0xe7,0x00,0x00,0x00,0x30,0x22]
 #CHECK: vlvgg   %v0, %r0, 4095          # encoding: [0xe7,0x00,0x0f,0xff,0x30,0x22]
 #CHECK: vlvgg   %v0, %r0, 0(%r15)       # encoding: [0xe7,0x00,0xf0,0x00,0x30,0x22]

llvm/test/MC/SystemZ/insn-good-z14.s

 # For z14 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z14 -show-encoding %s \
 # RUN:   | FileCheck %s
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch12 -show-encoding %s \
 # RUN:   | FileCheck %s
 
 #CHECK: agh %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38]
 #CHECK: agh %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38]
 #CHECK: agh %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38]
 #CHECK: agh %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38]
 #CHECK: agh %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38]
 #CHECK: agh %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38]
 #CHECK: agh %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38]
 #CHECK: agh %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38]
 #CHECK: agh %r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38]
 #CHECK: agh %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38]
+#CHECK: agh %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38]
+#CHECK: agh %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38]
+#CHECK: agh %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38]
+#CHECK: agh %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38]
+#CHECK: agh %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38]
+#CHECK: agh %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38]
+#CHECK: agh %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38]
+#CHECK: agh %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38]
+#CHECK: agh %r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38]
+#CHECK: agh %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38]
 
   agh %r0, -524288
   agh %r0, -1
   agh %r0, 0
   agh %r0, 1
   agh %r0, 524287
   agh %r0, 0(%r1)
   agh %r0, 0(%r15)
   agh %r0, 524287(%r1,%r15)
   agh %r0, 524287(%r15,%r1)
   agh %r15, 0
+  agh 0, -524288
+  agh 0, -1
+  agh 0, 0
+  agh 0, 1
+  agh 0, 524287
+  agh 0, 0(1)
+  agh 0, 0(15)
+  agh 0, 524287(1,15)
+  agh 0, 524287(15,1)
+  agh 15, 0
 
 #CHECK: bi  -524288                 # encoding: [0xe3,0xf0,0x00,0x00,0x80,0x47]
 #CHECK: bi  -1                      # encoding: [0xe3,0xf0,0x0f,0xff,0xff,0x47]
 #CHECK: bi  0                       # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x47]
 #CHECK: bi  1                       # encoding: [0xe3,0xf0,0x00,0x01,0x00,0x47]
 #CHECK: bi  524287                  # encoding: [0xe3,0xf0,0x0f,0xff,0x7f,0x47]
 #CHECK: bi  0(%r1)                  # encoding: [0xe3,0xf0,0x10,0x00,0x00,0x47]
 #CHECK: bi  0(%r15)                 # encoding: [0xe3,0xf0,0xf0,0x00,0x00,0x47]

 
 #CHECK: vllezlf %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x60,0x04]
 #CHECK: vllezlf %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x60,0x04]
 #CHECK: vllezlf %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x60,0x04]
 #CHECK: vllezlf %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x60,0x04]
 #CHECK: vllezlf %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x60,0x04]
 #CHECK: vllezlf %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x68,0x04]
 #CHECK: vllezlf %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x68,0x04]
+#CHECK: vllezlf %v0, 0                  # encoding: [0xe7,0x00,0x00,0x00,0x60,0x04]
+#CHECK: vllezlf %v0, 4095               # encoding: [0xe7,0x00,0x0f,0xff,0x60,0x04]
+#CHECK: vllezlf %v0, 0(%r15)            # encoding: [0xe7,0x00,0xf0,0x00,0x60,0x04]
+#CHECK: vllezlf %v0, 0(%r15,%r1)        # encoding: [0xe7,0x0f,0x10,0x00,0x60,0x04]
+#CHECK: vllezlf %v15, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x60,0x04]
+#CHECK: vllezlf %v31, 0                 # encoding: [0xe7,0xf0,0x00,0x00,0x68,0x04]
+#CHECK: vllezlf %v18, 1383(%r3,%r4)     # encoding: [0xe7,0x23,0x45,0x67,0x68,0x04]
 
   vllezlf %v0, 0
   vllezlf %v0, 4095
   vllezlf %v0, 0(%r15)
   vllezlf %v0, 0(%r15,%r1)
   vllezlf %v15, 0
   vllezlf %v31, 0
   vllezlf %v18, 0x567(%r3,%r4)
+  vllezlf 0, 0
+  vllezlf 0, 4095
+  vllezlf 0, 0(15)
+  vllezlf 0, 0(15,1)
+  vllezlf 15, 0
+  vllezlf 31, 0
+  vllezlf 18, 0x567(3,4)
 
 #CHECK: vlrl  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x35]
 #CHECK: vlrl  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x35]
 #CHECK: vlrl  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x35]
 #CHECK: vlrl  %v0, 0, 255             # encoding: [0xe6,0xff,0x00,0x00,0x00,0x35]
 #CHECK: vlrl  %v15, 0, 0              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x35]
 #CHECK: vlrl  %v31, 0, 0              # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x35]
 #CHECK: vlrl  %v18, 1383(%r4), 3      # encoding: [0xe6,0x03,0x45,0x67,0x21,0x35]
+#CHECK: vlrl  %v0, 0, 0               # encoding: [0xe6,0x00,0x00,0x00,0x00,0x35]
+#CHECK: vlrl  %v0, 4095, 0            # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x35]
+#CHECK: vlrl  %v0, 0(%r15), 0         # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x35]
+#CHECK: vlrl  %v0, 0, 255             # encoding: [0xe6,0xff,0x00,0x00,0x00,0x35]
+#CHECK: vlrl  %v15, 0, 0              # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x35]
+#CHECK: vlrl  %v31, 0, 0              # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x35]
+#CHECK: vlrl  %v18, 1383(%r4), 3      # encoding: [0xe6,0x03,0x45,0x67,0x21,0x35]
 
   vlrl  %v0, 0, 0
   vlrl  %v0, 4095, 0
   vlrl  %v0, 0(%r15), 0
   vlrl  %v0, 0, 255
   vlrl  %v15, 0, 0
   vlrl  %v31, 0, 0
   vlrl  %v18, 1383(%r4), 3
+  vlrl  0, 0, 0
+  vlrl  0, 4095, 0
+  vlrl  0, 0(15), 0
+  vlrl  0, 0, 255
+  vlrl  15, 0, 0
+  vlrl  31, 0, 0
+  vlrl  18, 1383(4), 3
 
 #CHECK: vlrlr %v0, %r0, 0             # encoding: [0xe6,0x00,0x00,0x00,0x00,0x37]
 #CHECK: vlrlr %v0, %r0, 4095          # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x37]
 #CHECK: vlrlr %v0, %r0, 0(%r15)       # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x37]
 #CHECK: vlrlr %v0, %r15, 0            # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x37]
 #CHECK: vlrlr %v15, %r0, 0            # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x37]
 #CHECK: vlrlr %v31, %r0, 0            # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x37]
 #CHECK: vlrlr %v18, %r3, 1383(%r4)    # encoding: [0xe6,0x03,0x45,0x67,0x21,0x37]

llvm/test/MC/SystemZ/insn-good-z15.s

 
 #CHECK: vllebrzg %v0, 0                 # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
 #CHECK: vllebrzg %v0, 4095              # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
 #CHECK: vllebrzg %v0, 0(%r15)           # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x04]
 #CHECK: vllebrzg %v0, 0(%r15,%r1)       # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x04]
 #CHECK: vllebrzg %v15, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x04]
 #CHECK: vllebrzg %v31, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
 #CHECK: vllebrzg %v18, 1383(%r3,%r4)    # encoding: [0xe6,0x23,0x45,0x67,0x38,0x04]
+#CHECK: vllebrzg %v0, 0                 # encoding: [0xe6,0x00,0x00,0x00,0x30,0x04]
+#CHECK: vllebrzg %v0, 4095              # encoding: [0xe6,0x00,0x0f,0xff,0x30,0x04]
+#CHECK: vllebrzg %v0, 0(%r15)           # encoding: [0xe6,0x00,0xf0,0x00,0x30,0x04]
+#CHECK: vllebrzg %v0, 0(%r15,%r1)       # encoding: [0xe6,0x0f,0x10,0x00,0x30,0x04]
+#CHECK: vllebrzg %v15, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x30,0x04]
+#CHECK: vllebrzg %v31, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x38,0x04]
+#CHECK: vllebrzg %v18, 1383(%r3,%r4)    # encoding: [0xe6,0x23,0x45,0x67,0x38,0x04]
 
   ldrv  %f0, 0
   ldrv  %f0, 4095
   ldrv  %f0, 0(%r15)
   ldrv  %f0, 0(%r15,%r1)
   ldrv  %f15, 0
   ldrv  %v31, 0
   ldrv  %v18, 0x567(%r3,%r4)
+  ldrv  0, 0
+  ldrv  0, 4095
+  ldrv  0, 0(15)
+  ldrv  0, 0(15,1)
+  ldrv  15, 0
+  ldrv  31, 0
+  ldrv  18, 0x567(3,4)
+
 
 #CHECK: vllebrze %v0, 0                 # encoding: [0xe6,0x00,0x00,0x00,0x60,0x04]
 #CHECK: vllebrze %v0, 4095              # encoding: [0xe6,0x00,0x0f,0xff,0x60,0x04]
 #CHECK: vllebrze %v0, 0(%r15)           # encoding: [0xe6,0x00,0xf0,0x00,0x60,0x04]
 #CHECK: vllebrze %v0, 0(%r15,%r1)       # encoding: [0xe6,0x0f,0x10,0x00,0x60,0x04]
 #CHECK: vllebrze %v15, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x60,0x04]
 #CHECK: vllebrze %v31, 0                # encoding: [0xe6,0xf0,0x00,0x00,0x68,0x04]
 #CHECK: vllebrze %v18, 1383(%r3,%r4)    # encoding: [0xe6,0x23,0x45,0x67,0x68,0x04]

llvm/test/MC/SystemZ/insn-good.s

 # For z10 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s
 
 #CHECK: a %r0, 0                  # encoding: [0x5a,0x00,0x00,0x00]
 #CHECK: a %r0, 4095               # encoding: [0x5a,0x00,0x0f,0xff]
 #CHECK: a %r0, 0(%r1)             # encoding: [0x5a,0x00,0x10,0x00]
 #CHECK: a %r0, 0(%r15)            # encoding: [0x5a,0x00,0xf0,0x00]
 #CHECK: a %r0, 4095(%r1,%r15)     # encoding: [0x5a,0x01,0xff,0xff]
 #CHECK: a %r0, 4095(%r15,%r1)     # encoding: [0x5a,0x0f,0x1f,0xff]
 #CHECK: a %r15, 0                 # encoding: [0x5a,0xf0,0x00,0x00]
+#CHECK: a %r0, 0                  # encoding: [0x5a,0x00,0x00,0x00]
+#CHECK: a %r0, 4095               # encoding: [0x5a,0x00,0x0f,0xff]
+#CHECK: a %r0, 0(%r1)             # encoding: [0x5a,0x00,0x10,0x00]
+#CHECK: a %r0, 0(%r15)            # encoding: [0x5a,0x00,0xf0,0x00]
+#CHECK: a %r0, 4095(%r1,%r15)     # encoding: [0x5a,0x01,0xff,0xff]
+#CHECK: a %r0, 4095(%r15,%r1)     # encoding: [0x5a,0x0f,0x1f,0xff]
+#CHECK: a %r15, 0                 # encoding: [0x5a,0xf0,0x00,0x00]
 
   a %r0, 0
   a %r0, 4095
   a %r0, 0(%r1)
   a %r0, 0(%r15)
   a %r0, 4095(%r1,%r15)
   a %r0, 4095(%r15,%r1)
   a %r15, 0
+  a 0, 0
+  a 0, 4095
+  a 0, 0(1)
+  a 0, 0(15)
+  a 0, 4095(1,15)
+  a 0, 4095(15,1)
+  a 15, 0
+
 
 #CHECK: ad  %f0, 0                  # encoding: [0x6a,0x00,0x00,0x00]
 #CHECK: ad  %f0, 4095               # encoding: [0x6a,0x00,0x0f,0xff]
 #CHECK: ad  %f0, 0(%r1)             # encoding: [0x6a,0x00,0x10,0x00]
 #CHECK: ad  %f0, 0(%r15)            # encoding: [0x6a,0x00,0xf0,0x00]
 #CHECK: ad  %f0, 4095(%r1,%r15)     # encoding: [0x6a,0x01,0xff,0xff]
 #CHECK: ad  %f0, 4095(%r15,%r1)     # encoding: [0x6a,0x0f,0x1f,0xff]
 #CHECK: ad  %f15, 0                 # encoding: [0x6a,0xf0,0x00,0x00]

 
 #CHECK: al  %r0, 0                  # encoding: [0x5e,0x00,0x00,0x00]
 #CHECK: al  %r0, 4095               # encoding: [0x5e,0x00,0x0f,0xff]
 #CHECK: al  %r0, 0(%r1)             # encoding: [0x5e,0x00,0x10,0x00]
 #CHECK: al  %r0, 0(%r15)            # encoding: [0x5e,0x00,0xf0,0x00]
 #CHECK: al  %r0, 4095(%r1,%r15)     # encoding: [0x5e,0x01,0xff,0xff]
 #CHECK: al  %r0, 4095(%r15,%r1)     # encoding: [0x5e,0x0f,0x1f,0xff]
 #CHECK: al  %r15, 0                 # encoding: [0x5e,0xf0,0x00,0x00]
+#CHECK: al  %r0, 0                  # encoding: [0x5e,0x00,0x00,0x00]
+#CHECK: al  %r0, 4095               # encoding: [0x5e,0x00,0x0f,0xff]
+#CHECK: al  %r0, 0(%r1)             # encoding: [0x5e,0x00,0x10,0x00]
+#CHECK: al  %r0, 0(%r15)            # encoding: [0x5e,0x00,0xf0,0x00]
+#CHECK: al  %r0, 4095(%r1,%r15)     # encoding: [0x5e,0x01,0xff,0xff]
+#CHECK: al  %r0, 4095(%r15,%r1)     # encoding: [0x5e,0x0f,0x1f,0xff]
+#CHECK: al  %r15, 0                 # encoding: [0x5e,0xf0,0x00,0x00]
 
   al  %r0, 0
   al  %r0, 4095
   al  %r0, 0(%r1)
   al  %r0, 0(%r15)
   al  %r0, 4095(%r1,%r15)
   al  %r0, 4095(%r15,%r1)
   al  %r15, 0
+  al  0, 0
+  al  0, 4095
+  al  0, 0(1)
+  al  0, 0(15)
+  al  0, 4095(1,15)
+  al  0, 4095(15,1)
+  al  15, 0
 
 #CHECK: alc %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x98]
 #CHECK: alc %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x98]
 #CHECK: alc %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x98]
 #CHECK: alc %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x98]
 #CHECK: alc %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x98]
 #CHECK: alc %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x98]
 #CHECK: alc %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x98]

 #CHECK: alg %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0a]
 #CHECK: alg %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0a]
 #CHECK: alg %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0a]
 #CHECK: alg %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0a]
 #CHECK: alg %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0a]
 #CHECK: alg %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0a]
 #CHECK: alg %r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0a]
 #CHECK: alg %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0a]
+#CHECK: alg %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0a]
+#CHECK: alg %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0a]
+#CHECK: alg %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0a]
+#CHECK: alg %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0a]
+#CHECK: alg %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0a]
+#CHECK: alg %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0a]
+#CHECK: alg %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0a]
+#CHECK: alg %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0a]
+#CHECK: alg %r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0a]
+#CHECK: alg %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0a]
 
   alg %r0, -524288
   alg %r0, -1
   alg %r0, 0
   alg %r0, 1
   alg %r0, 524287
   alg %r0, 0(%r1)
   alg %r0, 0(%r15)
   alg %r0, 524287(%r1,%r15)
   alg %r0, 524287(%r15,%r1)
   alg %r15, 0
+  alg 0, -524288
+  alg 0, -1
+  alg 0, 0
+  alg 0, 1
+  alg 0, 524287
+  alg 0, 0(1)
+  alg 0, 0(15)
+  alg 0, 524287(1,15)
+  alg 0, 524287(15,1)
+  alg 15, 0
 
 #CHECK: algf  %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1a]
 #CHECK: algf  %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1a]
 #CHECK: algf  %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x1a]
 #CHECK: algf  %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x1a]
 #CHECK: algf  %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x1a]
 #CHECK: algf  %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x1a]
 #CHECK: algf  %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x1a]

 #CHECK: algsi 0, -128                 # encoding: [0xeb,0x80,0x00,0x00,0x00,0x7e]
 #CHECK: algsi 0, -1                   # encoding: [0xeb,0xff,0x00,0x00,0x00,0x7e]
 #CHECK: algsi 0, 1                    # encoding: [0xeb,0x01,0x00,0x00,0x00,0x7e]
 #CHECK: algsi 0, 127                  # encoding: [0xeb,0x7f,0x00,0x00,0x00,0x7e]
 #CHECK: algsi 0(%r1), 42              # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x7e]
 #CHECK: algsi 0(%r15), 42             # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x7e]
 #CHECK: algsi 524287(%r1), 42         # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x7e]
 #CHECK: algsi 524287(%r15), 42        # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x7e]
+#CHECK: algsi -524288, 0              # encoding: [0xeb,0x00,0x00,0x00,0x80,0x7e]
+#CHECK: algsi -1, 0                   # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x7e]
+#CHECK: algsi 0, 0                    # encoding: [0xeb,0x00,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 1, 0                    # encoding: [0xeb,0x00,0x00,0x01,0x00,0x7e]
+#CHECK: algsi 524287, 0               # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x7e]
+#CHECK: algsi 0, -128                 # encoding: [0xeb,0x80,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0, -1                   # encoding: [0xeb,0xff,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0, 1                    # encoding: [0xeb,0x01,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0, 127                  # encoding: [0xeb,0x7f,0x00,0x00,0x00,0x7e]
+#CHECK: algsi 0(%r1), 42              # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x7e]
+#CHECK: algsi 0(%r15), 42             # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x7e]
+#CHECK: algsi 524287(%r1), 42         # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x7e]
+#CHECK: algsi 524287(%r15), 42        # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x7e]
 
   algsi -524288, 0
   algsi -1, 0
   algsi 0, 0
   algsi 1, 0
   algsi 524287, 0
   algsi 0, -128
   algsi 0, -1
   algsi 0, 1
   algsi 0, 127
   algsi 0(%r1), 42
   algsi 0(%r15), 42
   algsi 524287(%r1), 42
   algsi 524287(%r15), 42
+  algsi -524288, 0
+  algsi -1, 0
+  algsi 0, 0
+  algsi 1, 0
+  algsi 524287, 0
+  algsi 0, -128
+  algsi 0, -1
+  algsi 0, 1
+  algsi 0, 127
+  algsi 0(1), 42
+  algsi 0(15), 42
+  algsi 524287(1), 42
+  algsi 524287(15), 42
 
 #CHECK: alr %r0, %r0                # encoding: [0x1e,0x00]
 #CHECK: alr %r0, %r15               # encoding: [0x1e,0x0f]
 #CHECK: alr %r15, %r0               # encoding: [0x1e,0xf0]
 #CHECK: alr %r7, %r8                # encoding: [0x1e,0x78]
 
   alr %r0,%r0
   alr %r0,%r15
#CHECK: ap  0(1), 0(16,%r15)        # encoding: [0xfa,0x0f,0x00,0x00,0xf0,0x00]
   ap  0(1,%r1), 0(1)
   ap  0(1,%r15), 0(1)
   ap  4095(1,%r1), 0(1)
   ap  4095(1,%r15), 0(1)
   ap  0(16,%r1), 0(1)
   ap  0(16,%r15), 0(1)
   ap  0(1), 0(16,%r1)
   ap  0(1), 0(16,%r15)
+  ap  0(1), 0(1)
+  ap  0(1), 0(1,1)
+  ap  0(1), 0(1,15)
+  ap  0(1), 4095(1)
+  ap  0(1), 4095(1,1)
+  ap  0(1), 4095(1,15)
+  ap  0(1,1), 0(1)
+  ap  0(1,15), 0(1)
+  ap  4095(1,1), 0(1)
+  ap  4095(1,15), 0(1)
+  ap  0(16,1), 0(1)
+  ap  0(16,15), 0(1)
+  ap  0(1), 0(16,1)
+  ap  0(1), 0(16,15)
 
 #CHECK: ar  %r0, %r0                # encoding: [0x1a,0x00]
 #CHECK: ar  %r0, %r15               # encoding: [0x1a,0x0f]
 #CHECK: ar  %r15, %r0               # encoding: [0x1a,0xf0]
 #CHECK: ar  %r7, %r8                # encoding: [0x1a,0x78]
 
   ar  %r0,%r0
   ar  %r0,%r15

llvm/test/MC/SystemZ/regs-good.s

#CHECK: lctl  %c0, %c15, 0            # encoding: [0xb7,0x0f,0x00,0x00]
   lctl  %c4,%c5,0
   lctl  %c6,%c7,0
   lctl  %c8,%c9,0
   lctl  %c10,%c11,0
   lctl  %c12,%c13,0
   lctl  %c14,%c15,0
   lctl  0,15,0
 
+#CHECK: st  %r0, 0                  # encoding: [0x50,0x00,0x00,0x00]
+#CHECK: st  %r0, 4095               # encoding: [0x50,0x00,0x0f,0xff]
+#CHECK: st  %r0, 0(%r1)             # encoding: [0x50,0x00,0x10,0x00]
+#CHECK: st  %r0, 0(%r15)            # encoding: [0x50,0x00,0xf0,0x00]
+#CHECK: st  %r0, 4095(%r1,%r15)     # encoding: [0x50,0x01,0xff,0xff]
+#CHECK: st  %r0, 4095(%r15,%r1)     # encoding: [0x50,0x0f,0x1f,0xff]
+#CHECK: st  %r15, 0                 # encoding: [0x50,0xf0,0x00,0x00]
+#CHECK: st  %r0, 0(%r1)             # encoding: [0x50,0x00,0x10,0x00]
+#CHECK: st  %r0, 0(%r15)            # encoding: [0x50,0x00,0xf0,0x00]
+#CHECK: st  %r0, 4095(%r1,%r15)     # encoding: [0x50,0x01,0xff,0xff]
+#CHECK: st  %r0, 4095(%r15,%r1)     # encoding: [0x50,0x0f,0x1f,0xff]
+
+  st  %r0, 0
+  st  %r0, 4095
+  st  %r0, 0(%r1)
+  st  %r0, 0(%r15)
+  st  %r0, 4095(%r1,%r15)
+  st  %r0, 4095(%r15,%r1)
+  st  %r15, 0
+  st  0, 0(1)
+  st  0, 0(15)
+  st  0, 4095(1,15)
+  st  0, 4095(15,1)
 
 #CHECK: .cfi_offset %r0, 0
 #CHECK: .cfi_offset %r1, 8
 #CHECK: .cfi_offset %r2, 16
 #CHECK: .cfi_offset %r3, 24
 #CHECK: .cfi_offset %r4, 32
 #CHECK: .cfi_offset %r5, 40
 #CHECK: .cfi_offset %r6, 48

llvm/test/MC/SystemZ/tokens.s

 #CHECK: error: invalid register
 #CHECK: foo %v32, 200
 #CHECK: error: invalid register
 #CHECK: foo %c, 200
 #CHECK: error: invalid register
 #CHECK: foo %, 200
 #CHECK: error: unknown token in expression
 #CHECK: foo {, 200
+#CHECK: error: invalid instruction
+#CHECK: foo 100(15), 300
+#CHECK: error: register expected
+#CHECK: foo 100(15,), 300
+#CHECK: error: invalid instruction
+#CHECK: foo 100(15,%r1), 300
+#CHECK: error: invalid instruction
+#CHECK: foo 100(%v20,10), 300
 
   foo 100, 200
   foo 100(, 200
   foo 100(200), 300
   foo 100(200,), 300
   foo 100(200,%r1), 300
   foo 100(%a0), 200
   foo 100(%r0), 200
#CHECK: foo 100(%v20,10), 300
   foo %a15, 200
   foo %a16, 200
   foo %v0, 200
   foo %v31, 200
   foo %v32, 200
   foo %c, 200
   foo %, 200
   foo {, 200
+  foo 100(15), 300
+  foo 100(15,), 300
+  foo 100(15,%r1), 300
+  foo 100(%v20,10), 300