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Differential D83058

[InstCombine] Add sext(ashr(shl(trunc(x),c),c)) folding support for vectors
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Authored by RKSimon on Jul 2 2020, 9:32 AM.

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spatel
lebedev.ri
Commits
rG3da42f48101f: [InstCombine] Add sext(ashr(shl(trunc(x),c),c)) folding support for vectors
Summary

Replacing m_ConstantInt with m_Constant permits folding of vectors as well as a scalars.

Diff Detail

Event Timeline

RKSimon created this revision.Jul 2 2020, 9:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 2 2020, 9:32 AM
Herald added a subscriber: hiraditya. · View Herald Transcript
Harbormaster completed remote builds in B62706: Diff 275149.Jul 2 2020, 10:14 AM
lebedev.ri accepted this revision.Jul 2 2020, 10:23 AM

LG, thank you.

This revision is now accepted and ready to land.Jul 2 2020, 10:23 AM
RKSimon retitled this revision from [InstCombine] Add sext(ashr(shl(trunc(x),c),c)) folding support for non-uniform vectors to [InstCombine] Add sext(ashr(shl(trunc(x),c),c)) folding support for vectors.Jul 2 2020, 11:16 AM
RKSimon edited the summary of this revision. (Show Details)
Closed by commit rG3da42f48101f: [InstCombine] Add sext(ashr(shl(trunc(x),c),c)) folding support for vectors (authored by RKSimon). · Explain WhyJul 3 2020, 2:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Transforms/
InstCombine/
15 lines
test/
Transforms/
InstCombine/
18 lines
15 lines

Diff 275149

llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp

Show First 20 Lines • Show All 1,454 Lines • ▼ Show 20 LinesInstruction *InstCombiner::visitSExt(SExtInst &CI) {
// %b = shl i8 %a, 6 // %b = shl i8 %a, 6
// %c = ashr i8 %b, 6 // %c = ashr i8 %b, 6
// %d = sext i8 %c to i32 // %d = sext i8 %c to i32
// into: // into:
// %a = shl i32 %i, 30 // %a = shl i32 %i, 30
// %d = ashr i32 %a, 30 // %d = ashr i32 %a, 30
Value *A = nullptr; Value *A = nullptr;
// TODO: Eventually this could be subsumed by EvaluateInDifferentType. // TODO: Eventually this could be subsumed by EvaluateInDifferentType.
ConstantInt *BA = nullptr, *CA = nullptr; Constant *BA = nullptr, *CA = nullptr;
if (match(Src, m_AShr(m_Shl(m_Trunc(m_Value(A)), m_ConstantInt(BA)), if (match(Src, m_AShr(m_Shl(m_Trunc(m_Value(A)), m_Constant(BA)),
m_ConstantInt(CA))) && m_Constant(CA))) &&
BA == CA && A->getType() == CI.getType()) { BA == CA && A->getType() == CI.getType()) {
unsigned MidSize = Src->getType()->getScalarSizeInBits(); unsigned MidSize = Src->getType()->getScalarSizeInBits();
unsigned SrcDstSize = CI.getType()->getScalarSizeInBits(); unsigned SrcDstSize = CI.getType()->getScalarSizeInBits();
unsigned ShAmt = CA->getZExtValue()+SrcDstSize-MidSize; Constant *SizeDiff = ConstantInt::get(CA->getType(), SrcDstSize - MidSize);
Constant *ShAmtV = ConstantInt::get(CI.getType(), ShAmt); Constant *ShAmt = ConstantExpr::getAdd(CA, SizeDiff);
A = Builder.CreateShl(A, ShAmtV, CI.getName()); Constant *ShAmtExt = ConstantExpr::getSExt(ShAmt, CI.getType());
return BinaryOperator::CreateAShr(A, ShAmtV); A = Builder.CreateShl(A, ShAmtExt, CI.getName());
return BinaryOperator::CreateAShr(A, ShAmtExt);
} }
return nullptr; return nullptr;
} }
/// Return a Constant* for the specified floating-point constant if it fits /// Return a Constant* for the specified floating-point constant if it fits
/// in the specified FP type without changing its value. /// in the specified FP type without changing its value.
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llvm/test/Transforms/InstCombine/sext.ll

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%B = shl i8 %A, 6 %B = shl i8 %A, 6
%C = ashr i8 %B, 6 %C = ashr i8 %B, 6
%D = sext i8 %C to i32 %D = sext i8 %C to i32
ret i32 %D ret i32 %D
} }
define <2 x i32> @test10_vec(<2 x i32> %i) { define <2 x i32> @test10_vec(<2 x i32> %i) {
; CHECK-LABEL: @test10_vec( ; CHECK-LABEL: @test10_vec(
; CHECK-NEXT: [[A:%.*]] = trunc <2 x i32> [[I:%.*]] to <2 x i8> ; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 30>
; CHECK-NEXT: [[B:%.*]] = shl <2 x i8> [[A]], <i8 6, i8 6> ; CHECK-NEXT: [[D:%.*]] = ashr exact <2 x i32> [[D1]], <i32 30, i32 30>
; CHECK-NEXT: [[C:%.*]] = ashr exact <2 x i8> [[B]], <i8 6, i8 6>
; CHECK-NEXT: [[D:%.*]] = sext <2 x i8> [[C]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[D]] ; CHECK-NEXT: ret <2 x i32> [[D]]
; ;
%A = trunc <2 x i32> %i to <2 x i8> %A = trunc <2 x i32> %i to <2 x i8>
%B = shl <2 x i8> %A, <i8 6, i8 6> %B = shl <2 x i8> %A, <i8 6, i8 6>
%C = ashr <2 x i8> %B, <i8 6, i8 6> %C = ashr <2 x i8> %B, <i8 6, i8 6>
%D = sext <2 x i8> %C to <2 x i32> %D = sext <2 x i8> %C to <2 x i32>
ret <2 x i32> %D ret <2 x i32> %D
} }
define <2 x i32> @test10_vec_nonuniform(<2 x i32> %i) { define <2 x i32> @test10_vec_nonuniform(<2 x i32> %i) {
; CHECK-LABEL: @test10_vec_nonuniform( ; CHECK-LABEL: @test10_vec_nonuniform(
; CHECK-NEXT: [[A:%.*]] = trunc <2 x i32> [[I:%.*]] to <2 x i8> ; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 27>
; CHECK-NEXT: [[B:%.*]] = shl <2 x i8> [[A]], <i8 6, i8 3> ; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[D1]], <i32 30, i32 27>
; CHECK-NEXT: [[C:%.*]] = ashr <2 x i8> [[B]], <i8 6, i8 3>
; CHECK-NEXT: [[D:%.*]] = sext <2 x i8> [[C]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[D]] ; CHECK-NEXT: ret <2 x i32> [[D]]
; ;
%A = trunc <2 x i32> %i to <2 x i8> %A = trunc <2 x i32> %i to <2 x i8>
%B = shl <2 x i8> %A, <i8 6, i8 3> %B = shl <2 x i8> %A, <i8 6, i8 3>
%C = ashr <2 x i8> %B, <i8 6, i8 3> %C = ashr <2 x i8> %B, <i8 6, i8 3>
%D = sext <2 x i8> %C to <2 x i32> %D = sext <2 x i8> %C to <2 x i32>
ret <2 x i32> %D ret <2 x i32> %D
} }
define <2 x i32> @test10_vec_undef(<2 x i32> %i) { define <2 x i32> @test10_vec_undef(<2 x i32> %i) {
; CHECK-LABEL: @test10_vec_undef( ; CHECK-LABEL: @test10_vec_undef(
; CHECK-NEXT: [[A:%.*]] = trunc <2 x i32> [[I:%.*]] to <2 x i8> ; CHECK-NEXT: [[D1:%.*]] = shl <2 x i32> [[I:%.*]], <i32 30, i32 0>
; CHECK-NEXT: [[B:%.*]] = shl <2 x i8> [[A]], <i8 6, i8 undef> ; CHECK-NEXT: [[D:%.*]] = ashr <2 x i32> [[D1]], <i32 30, i32 0>
; CHECK-NEXT: [[C:%.*]] = ashr <2 x i8> [[B]], <i8 6, i8 undef>
; CHECK-NEXT: [[D:%.*]] = sext <2 x i8> [[C]] to <2 x i32>
; CHECK-NEXT: ret <2 x i32> [[D]] ; CHECK-NEXT: ret <2 x i32> [[D]]
; ;
%A = trunc <2 x i32> %i to <2 x i8> %A = trunc <2 x i32> %i to <2 x i8>
%B = shl <2 x i8> %A, <i8 6, i8 undef> %B = shl <2 x i8> %A, <i8 6, i8 undef>
%C = ashr <2 x i8> %B, <i8 6, i8 undef> %C = ashr <2 x i8> %B, <i8 6, i8 undef>
%D = sext <2 x i8> %C to <2 x i32> %D = sext <2 x i8> %C to <2 x i32>
ret <2 x i32> %D ret <2 x i32> %D
} }
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llvm/test/Transforms/InstCombine/trunc.ll

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%d = sext i32 %q to i64 %d = sext i32 %q to i64
call void @use(i32 %b) call void @use(i32 %b)
ret i64 %d ret i64 %d
} }
define <2 x i64> @test2_vec(<2 x i64> %a) { define <2 x i64> @test2_vec(<2 x i64> %a) {
; CHECK-LABEL: @test2_vec( ; CHECK-LABEL: @test2_vec(
; CHECK-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32> ; CHECK-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32>
; CHECK-NEXT: [[C:%.*]] = shl <2 x i32> [[B]], <i32 4, i32 4> ; CHECK-NEXT: [[D1:%.*]] = shl <2 x i64> [[A]], <i64 36, i64 36>
; CHECK-NEXT: [[Q:%.*]] = ashr exact <2 x i32> [[C]], <i32 4, i32 4> ; CHECK-NEXT: [[D:%.*]] = ashr exact <2 x i64> [[D1]], <i64 36, i64 36>
; CHECK-NEXT: [[D:%.*]] = sext <2 x i32> [[Q]] to <2 x i64>
; CHECK-NEXT: call void @use_vec(<2 x i32> [[B]]) ; CHECK-NEXT: call void @use_vec(<2 x i32> [[B]])
; CHECK-NEXT: ret <2 x i64> [[D]] ; CHECK-NEXT: ret <2 x i64> [[D]]
; ;
%b = trunc <2 x i64> %a to <2 x i32> %b = trunc <2 x i64> %a to <2 x i32>
%c = shl <2 x i32> %b, <i32 4, i32 4> %c = shl <2 x i32> %b, <i32 4, i32 4>
%q = ashr <2 x i32> %c, <i32 4, i32 4> %q = ashr <2 x i32> %c, <i32 4, i32 4>
%d = sext <2 x i32> %q to <2 x i64> %d = sext <2 x i32> %q to <2 x i64>
call void @use_vec(<2 x i32> %b) call void @use_vec(<2 x i32> %b)
ret <2 x i64> %d ret <2 x i64> %d
} }
define <2 x i64> @test2_vec_nonuniform(<2 x i64> %a) { define <2 x i64> @test2_vec_nonuniform(<2 x i64> %a) {
; CHECK-LABEL: @test2_vec_nonuniform( ; CHECK-LABEL: @test2_vec_nonuniform(
; CHECK-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32> ; CHECK-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32>
; CHECK-NEXT: [[C:%.*]] = shl <2 x i32> [[B]], <i32 4, i32 5> ; CHECK-NEXT: [[D1:%.*]] = shl <2 x i64> [[A]], <i64 36, i64 37>
; CHECK-NEXT: [[Q:%.*]] = ashr <2 x i32> [[C]], <i32 4, i32 5> ; CHECK-NEXT: [[D:%.*]] = ashr <2 x i64> [[D1]], <i64 36, i64 37>
; CHECK-NEXT: [[D:%.*]] = sext <2 x i32> [[Q]] to <2 x i64>
; CHECK-NEXT: call void @use_vec(<2 x i32> [[B]]) ; CHECK-NEXT: call void @use_vec(<2 x i32> [[B]])
; CHECK-NEXT: ret <2 x i64> [[D]] ; CHECK-NEXT: ret <2 x i64> [[D]]
; ;
%b = trunc <2 x i64> %a to <2 x i32> %b = trunc <2 x i64> %a to <2 x i32>
%c = shl <2 x i32> %b, <i32 4, i32 5> %c = shl <2 x i32> %b, <i32 4, i32 5>
%q = ashr <2 x i32> %c, <i32 4, i32 5> %q = ashr <2 x i32> %c, <i32 4, i32 5>
%d = sext <2 x i32> %q to <2 x i64> %d = sext <2 x i32> %q to <2 x i64>
call void @use_vec(<2 x i32> %b) call void @use_vec(<2 x i32> %b)
ret <2 x i64> %d ret <2 x i64> %d
} }
define <2 x i64> @test2_vec_undef(<2 x i64> %a) { define <2 x i64> @test2_vec_undef(<2 x i64> %a) {
; CHECK-LABEL: @test2_vec_undef( ; CHECK-LABEL: @test2_vec_undef(
; CHECK-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32> ; CHECK-NEXT: [[B:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i32>
; CHECK-NEXT: [[C:%.*]] = shl <2 x i32> [[B]], <i32 4, i32 undef> ; CHECK-NEXT: [[D1:%.*]] = shl <2 x i64> [[A]], <i64 36, i64 0>
; CHECK-NEXT: [[Q:%.*]] = ashr <2 x i32> [[C]], <i32 4, i32 undef> ; CHECK-NEXT: [[D:%.*]] = ashr <2 x i64> [[D1]], <i64 36, i64 0>
; CHECK-NEXT: [[D:%.*]] = sext <2 x i32> [[Q]] to <2 x i64>
; CHECK-NEXT: call void @use_vec(<2 x i32> [[B]]) ; CHECK-NEXT: call void @use_vec(<2 x i32> [[B]])
; CHECK-NEXT: ret <2 x i64> [[D]] ; CHECK-NEXT: ret <2 x i64> [[D]]
; ;
%b = trunc <2 x i64> %a to <2 x i32> %b = trunc <2 x i64> %a to <2 x i32>
%c = shl <2 x i32> %b, <i32 4, i32 undef> %c = shl <2 x i32> %b, <i32 4, i32 undef>
%q = ashr <2 x i32> %c, <i32 4, i32 undef> %q = ashr <2 x i32> %c, <i32 4, i32 undef>
%d = sext <2 x i32> %q to <2 x i64> %d = sext <2 x i32> %q to <2 x i64>
call void @use_vec(<2 x i32> %b) call void @use_vec(<2 x i32> %b)
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