[PowerPC][Power10] Add Vector Splat Immediate, Permute, Blend, Shift Double Bit immediate Instruction Definitions and MC Tests

[amyk]

Summary

This patch adds the td definitions and asm/disasm tests for the following instructions:

XXSPLTIW
XXSPLTIDP
XXSPLTI32DX

XXPERMX

XXBLENDVB
XXBLENDVH
XXBLENDVW
XXBLENDVD

VSLDBI
VSRDBI

[lei]

LGTM other then the minor nit that can be address on commit.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

331

nit... wondering if we can reorder this 2 class def so its:

class 8RR_XX4_XTABC6
....
class 8RR_XX4_IMM3_XTABC6
...

Seems like the class defined on line 180 class 8RR_XX4Form_IMM8_XTAB6 should of been named class 8RR_XX4Form_IMM8_XTABC6?

If so it would be good if these are defined in order.
What's the diff in XX4 vs XX4Form in the naming?

[amyk]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

331

Sure, I can reorder it so the IMM version comes after.
I believe XX4 and XX4Form is referring to the same form. I think it's likely we forgot to put Form.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
 
   let Inst{6-10}  = RD;
   let Inst{11-12} = 0;
   let Inst{13-15} = N;
   let Inst{16-20} = VB;
   let Inst{21-31} = xo;
 }
 
+// VN-Form: [PO VRT VRA VRB PS SD XO]
+// SD is "Shift Direction"
+class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
+                       InstrItinClass itin, list<dag> pattern>
+    : I<4, OOL, IOL, asmstr, itin> {
+  bits<5> VRT;
+  bits<5> VRA;
+  bits<5> VRB;
+  bits<3> SD;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = VRT;
+  let Inst{11-15} = VRA;
+  let Inst{16-20} = VRB;
+  let Inst{21-22} = ps;
+  let Inst{23-25} = SD;
+  let Inst{26-31} = xo;
+}
+
+// 8RR:D-Form: [ 1 1 0 // // imm0
+//               PO T XO TX imm1 ].
+class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
+                          string asmstr, InstrItinClass itin,
+                          list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<32> IMM32;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1;
+  let Inst{8-11} = 0;
+  let Inst{12-13} = 0; // reserved
+  let Inst{14-15} = 0; // reserved
+  let Inst{16-31} = IMM32{31-16};
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-46} = xo;
+  let Inst{47} = XT{5};
+  let Inst{48-63} = IMM32{15-0};
+}
+
+// 8RR:D-Form: [ 1 1 0 // // imm0
+//               PO T XO IX TX imm1 ].
+class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
+                             string asmstr, InstrItinClass itin,
+                             list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bit IX;
+  bits<32> IMM32;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1;
+  let Inst{8-11} = 0;
+  let Inst{12-13} = 0; // reserved
+  let Inst{14-15} = 0; // reserved
+  let Inst{16-31} = IMM32{31-16};
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-45} = xo;
+  let Inst{46} = IX;
+  let Inst{47} = XT{5};
+  let Inst{48-63} = IMM32{15-0};
+}
+
+class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
+                         string asmstr, InstrItinClass itin, list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XA;
+  bits<6> XB;
+  bits<6> XC;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1;
+  let Inst{8-11} = 0;
+  let Inst{12-13} = 0;
+  let Inst{14-31} = 0;
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-47} = XA{4-0};
+  let Inst{48-52} = XB{4-0};
+  let Inst{53-57} = XC{4-0};
+  let Inst{58-59} = xo;
+  let Inst{60} = XC{5};
+  let Inst{61} = XA{5};
+  let Inst{62} = XB{5};
+  let Inst{63} = XT{5};
+}
+
+class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
+                              string asmstr, InstrItinClass itin,
+                              list<dag> pattern>
+  : PI<1, opcode, OOL, IOL, asmstr, itin> {
+  bits<6> XT;
+  bits<6> XA;
+  bits<6> XB;
+  bits<6> XC;
+  bits<3> IMM;
+
+  let Pattern = pattern;
+
+  // The prefix.
+  let Inst{6-7} = 1;
+  let Inst{8-11} = 0;
+  let Inst{12-13} = 0;
+  let Inst{14-28} = 0;
+  let Inst{29-31} = IMM;
+
+  // The instruction.
+  let Inst{38-42} = XT{4-0};
+  let Inst{43-47} = XA{4-0};
+  let Inst{48-52} = XB{4-0};
+  let Inst{53-57} = XC{4-0};
+  let Inst{58-59} = xo;
+  let Inst{60} = XC{5};
+  let Inst{61} = XA{5};
+  let Inst{62} = XB{5};
+  let Inst{63} = XT{5};
+}
+
 multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
                                        dag PCRel_IOL, string asmstr,
                                        InstrItinClass itin> {
   def NAME : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, IOL,
                                        !strconcat(asmstr, ", 0"), itin, []>;
   def pc : MLS_DForm_R_SI34_RTA5_MEM<opcode, OOL, PCRel_IOL,
                                      !strconcat(asmstr, ", 1"), itin, []>,
                                      isPCRel;
def : Pat<(PPCstore_scal_int_from_vsr
               (PPCmatpcreladdr pcreladdr:$dst), 8),
             (PSTXSDpc (COPY_TO_REGCLASS (XSCVQPUDZ f128:$src), VFRC), $dst, 0)>;
 
   // If the PPCmatpcreladdr node is not caught by any other pattern it should be
   // caught here and turned into a paddi instruction to materialize the address.
   def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
 }
 
+let Predicates = [PrefixInstrs] in {
+  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
+                                     (ins i32imm:$IMM32),
+                                     "xxspltiw $XT, $IMM32", IIC_VecGeneral,
+                                     []>;
+  def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
+                                      (ins i32imm:$IMM32),
+                                      "xxspltidp $XT, $IMM32", IIC_VecGeneral,
+                                      []>;
+  def XXSPLTI32DX :
+      8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
+                             (ins vsrc:$XTi, i1imm:$IX, i32imm:$IMM32),
+                             "xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, []>,
+                             RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
+  def XXPERMX :
+    8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
+                            vsrc:$XC, u3imm:$UIM),
+                            "xxpermx $XT, $XA, $XB, $XC, $UIM",
+                            IIC_VecPerm, []>;
+  def XXBLENDVB :
+    8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
+                       vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
+                       IIC_VecGeneral, []>;
+  def XXBLENDVH :
+    8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
+                       vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
+                       IIC_VecGeneral, []>;
+  def XXBLENDVW :
+    8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
+                       vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
+                       IIC_VecGeneral, []>;
+  def XXBLENDVD :
+    8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
+                       vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
+                       IIC_VecGeneral, []>;
+}
+
 let Predicates = [IsISA3_1] in {
+  def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
+                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
+                                "vsldbi $VRT, $VRA, $VRB, $SH",
+                                IIC_VecGeneral, []>;
+  def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
+                                (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
+                                "vsrdbi $VRT, $VRA, $VRB, $SH",
+                                IIC_VecGeneral, []>;
    def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
    def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpextd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;

llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt

 # CHECK xxgenpcvdm 0, 1, 2
 0xf0 0x02 0x0f 0x6a
 
 # CHECK: vclrlb 1, 4, 3
 0x10 0x24 0x19 0x8d
 
 # CHECK: vclrrb 1, 4, 3
 0x10 0x24 0x19 0xcd
+
+# Boundary conditions of 8RR_DForm_IMM32_XT6's immediates
+# CHECK: xxspltiw 63, 4294901760
+0x05 0x00 0xff 0xff 0x83 0xe7 0x00 0x00
+
+# CHECK: xxspltiw 63, 65535
+0x05 0x00 0x00 0x00 0x83 0xe7 0xff 0xff
+
+# CHECK: xxspltiw 63, 4294967295
+0x05 0x00 0xff 0xff 0x83 0xe7 0xff 0xff
+
+# CHECK: xxspltidp 63, 4294967295
+0x05 0x00 0xff 0xff 0x83 0xe5 0xff 0xff
+
+# Boundary conditions of 8RR_DForm_IMM32_XT6_IX's immediates
+# CHECK: xxsplti32dx 63, 1, 4294901760
+0x05 0x00 0xff 0xff 0x83 0xe3 0x00 0x00
+
+# CHECK: xxsplti32dx 63, 1, 65535
+0x05 0x00 0x00 0x00 0x83 0xe3 0xff 0xff
+
+# CHECK: xxsplti32dx 63, 1, 4294967295
+0x05 0x00 0xff 0xff 0x83 0xe3 0xff 0xff
+
+# CHECK: xxpermx 6, 63, 21, 34, 2
+0x05 0x00 0x00 0x02 0x88 0xdf 0xa8 0x8c
+
+# CHECK: xxblendvb 6, 63, 21, 34
+0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0x8c
+
+# CHECK: xxblendvh 6, 63, 21, 34
+0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0x9c
+
+# CHECK: xxblendvw 6, 63, 21, 34
+0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xac
+
+# CHECK: xxblendvd 6, 63, 21, 34
+0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc
+
+# CHECK: vsldbi 2, 3, 4, 5
+0x10 0x43 0x21 0x56
+
+# CHECK: vsrdbi 2, 3, 4, 5
+0x10 0x43 0x23 0x56

llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s

 # CHECK-LE: xxgenpcvdm 0, 1, 2                    # encoding: [0x6a,0x0f,0x02,0xf0]
             xxgenpcvdm 0, 1, 2
 # CHECK-BE: vclrlb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0x8d]
 # CHECK-LE: vclrlb 1, 4, 3                        # encoding: [0x8d,0x19,0x24,0x10]
             vclrlb 1, 4, 3
 # CHECK-BE: vclrrb 1, 4, 3                        # encoding: [0x10,0x24,0x19,0xcd]
 # CHECK-LE: vclrrb 1, 4, 3                        # encoding: [0xcd,0x19,0x24,0x10]
             vclrrb 1, 4, 3
+# Boundary conditions of 8RR_DForm_IMM32_XT6's immediates
+# CHECK-BE: xxspltiw 63, 4294901760               # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe7,0x00,0x00]
+# CHECK-LE: xxspltiw 63, 4294901760               # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0x00,0x00,0xe7,0x83]
+            xxspltiw 63, 4294901760
+# CHECK-BE: xxspltiw 63, 65535                    # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                               0x83,0xe7,0xff,0xff]
+# CHECK-LE: xxspltiw 63, 65535                    # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe7,0x83]
+            xxspltiw 63, 65535
+# CHECK-BE: xxspltiw 63, 4294967295               # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe7,0xff,0xff]
+# CHECK-LE: xxspltiw 63, 4294967295               # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe7,0x83]
+            xxspltiw 63, 4294967295
+# CHECK-BE: xxspltiw 63, -1                       # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe7,0xff,0xff]
+# CHECK-LE: xxspltiw 63, -1                       # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe7,0x83]
+            xxspltiw 63, -1
+# CHECK-BE: xxspltidp 63, 4294967295              # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe5,0xff,0xff]
+# CHECK-LE: xxspltidp 63, 4294967295              # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe5,0x83]
+            xxspltidp 63, 4294967295
+# Boundary conditions of 8RR_DForm_IMM32_XT6_IX's immediates
+# CHECK-BE: xxsplti32dx 63, 1, 4294901760         # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe3,0x00,0x00]
+# CHECK-LE: xxsplti32dx 63, 1, 4294901760         # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0x00,0x00,0xe3,0x83]
+            xxsplti32dx 63, 1, 4294901760
+# CHECK-BE: xxsplti32dx 63, 1, 65535              # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                               0x83,0xe3,0xff,0xff]
+# CHECK-LE: xxsplti32dx 63, 1, 65535              # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe3,0x83]
+            xxsplti32dx 63, 1, 65535
+# CHECK-BE: xxsplti32dx 63, 1, 4294967295         # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe3,0xff,0xff]
+# CHECK-LE: xxsplti32dx 63, 1, 4294967295         # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe3,0x83]
+            xxsplti32dx 63, 1, 4294967295
+# CHECK-BE: xxsplti32dx 63, 1, -1                 # encoding: [0x05,0x00,0xff,0xff,
+# CHECK-BE-SAME:                                               0x83,0xe3,0xff,0xff]
+# CHECK-LE: xxsplti32dx 63, 1, -1                 # encoding: [0xff,0xff,0x00,0x05,
+# CHECK-LE-SAME:                                               0xff,0xff,0xe3,0x83]
+            xxsplti32dx 63, 1, -1
+# CHECK-BE: xxpermx 6, 63, 21, 34, 2              # encoding: [0x05,0x00,0x00,0x02,
+# CHECK-BE-SAME:                                               0x88,0xdf,0xa8,0x8c]
+# CHECK-LE: xxpermx 6, 63, 21, 34, 2              # encoding: [0x02,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0x8c,0xa8,0xdf,0x88]
+            xxpermx 6, 63, 21, 34, 2
+# CHECK-BE: xxblendvb 6, 63, 21, 34               # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                               0x84,0xdf,0xa8,0x8c]
+# CHECK-LE: xxblendvb 6, 63, 21, 34               # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0x8c,0xa8,0xdf,0x84]
+            xxblendvb 6, 63, 21, 34
+# CHECK-BE: xxblendvh 6, 63, 21, 34               # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                               0x84,0xdf,0xa8,0x9c]
+# CHECK-LE: xxblendvh 6, 63, 21, 34               # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0x9c,0xa8,0xdf,0x84]
+            xxblendvh 6, 63, 21, 34
+# CHECK-BE: xxblendvw 6, 63, 21, 34               # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                               0x84,0xdf,0xa8,0xac]
+# CHECK-LE: xxblendvw 6, 63, 21, 34               # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0xac,0xa8,0xdf,0x84]
+            xxblendvw 6, 63, 21, 34
+# CHECK-BE: xxblendvd 6, 63, 21, 34               # encoding: [0x05,0x00,0x00,0x00,
+# CHECK-BE-SAME:                                               0x84,0xdf,0xa8,0xbc]
+# CHECK-LE: xxblendvd 6, 63, 21, 34               # encoding: [0x00,0x00,0x00,0x05,
+# CHECK-LE-SAME:                                               0xbc,0xa8,0xdf,0x84]
+            xxblendvd 6, 63, 21, 34
+# CHECK-BE: vsldbi 2, 3, 4, 5                     # encoding: [0x10,0x43,0x21,0x56]
+# CHECK-LE: vsldbi 2, 3, 4, 5                     # encoding: [0x56,0x21,0x43,0x10]
+            vsldbi 2, 3, 4, 5
+# CHECK-BE: vsrdbi 2, 3, 4, 5                     # encoding: [0x10,0x43,0x23,0x56]
+# CHECK-LE: vsrdbi 2, 3, 4, 5                     # encoding: [0x56,0x23,0x43,0x10]
+            vsrdbi 2, 3, 4, 5