Fix tail allocation for large static alloca

[serge-sans-paille]

llvm/test/CodeGen/X86/stack-clash-large.ll

46

This mov wasn't relevant, as %r11d was clipped.

[cuviper]

llvm/test/CodeGen/X86/stack-clash-large.ll

24–25

I think this condition is also backwards -- in AT&T syntax, this will jump when %rsp<%r11, which is immediately false.

[serge-sans-paille]

llvm/test/CodeGen/X86/stack-clash-large.ll

24–25

this could even be a jne, I guess.

[cuviper]

llvm/test/CodeGen/X86/stack-clash-large.ll

24–25

Yeah, jne should work. Maybe rename FinalStackPtr to something like FinalStackProbe too, so it's clear that doesn't include the remainder.

[serge-sans-paille]

Take review into account: fix check.

[serge-sans-paille]

@cupiver. It should be okay for static allocations now.

[cuviper]

LGTM, and I confirmed that it works in a full rustc bootstrap, thanks!

llvm/lib/Target/X86/X86FrameLowering.cpp

void X86FrameLowering::emitStackProbeInlineGenericLoop(
 
   MachineBasicBlock *testMBB = MF.CreateMachineBasicBlock(LLVM_BB);
   MachineBasicBlock *tailMBB = MF.CreateMachineBasicBlock(LLVM_BB);
 
   MachineFunction::iterator MBBIter = ++MBB.getIterator();
   MF.insert(MBBIter, testMBB);
   MF.insert(MBBIter, tailMBB);
 
-  Register FinalStackPtr = Uses64BitFramePtr ? X86::R11 : X86::R11D;
-  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::COPY), FinalStackPtr)
+  Register FinalStackProbed = Uses64BitFramePtr ? X86::R11 : X86::R11D;
+  BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::COPY), FinalStackProbed)
       .addReg(StackPtr)
       .setMIFlag(MachineInstr::FrameSetup);
 
   // save loop bound
   {
     const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, Offset);
-    BuildMI(MBB, MBBI, DL, TII.get(Opc), FinalStackPtr)
-        .addReg(FinalStackPtr)
+    BuildMI(MBB, MBBI, DL, TII.get(Opc), FinalStackProbed)
+        .addReg(FinalStackProbed)
         .addImm(Offset / StackProbeSize * StackProbeSize)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // allocate a page
   {
     const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, StackProbeSize);
     BuildMI(testMBB, DL, TII.get(Opc), StackPtr)
         .addReg(StackPtr)
         .addImm(StackProbeSize)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // touch the page
   addRegOffset(BuildMI(testMBB, DL, TII.get(MovMIOpc))
                    .setMIFlag(MachineInstr::FrameSetup),
                StackPtr, false, 0)
       .addImm(0)
       .setMIFlag(MachineInstr::FrameSetup);
 
   // cmp with stack pointer bound
   BuildMI(testMBB, DL, TII.get(Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
       .addReg(StackPtr)
-      .addReg(FinalStackPtr)
+      .addReg(FinalStackProbed)
       .setMIFlag(MachineInstr::FrameSetup);
 
   // jump
   BuildMI(testMBB, DL, TII.get(X86::JCC_1))
       .addMBB(testMBB)
-      .addImm(X86::COND_L)
+      .addImm(X86::COND_NE)
       .setMIFlag(MachineInstr::FrameSetup);
   testMBB->addSuccessor(testMBB);
   testMBB->addSuccessor(tailMBB);
 
   // BB management
   tailMBB->splice(tailMBB->end(), &MBB, MBBI, MBB.end());
   tailMBB->transferSuccessorsAndUpdatePHIs(&MBB);
   MBB.addSuccessor(testMBB);
 
   // handle tail
-  if (Offset % StackProbeSize) {
-    BuildMI(*tailMBB, tailMBB->begin(), DL, TII.get(TargetOpcode::COPY),
-            StackPtr)
-        .addReg(FinalStackPtr)
+  unsigned TailOffset = Offset % StackProbeSize;
+  if (TailOffset) {
+    const unsigned Opc = getSUBriOpcode(Uses64BitFramePtr, TailOffset);
+    BuildMI(*tailMBB, tailMBB->begin(), DL, TII.get(Opc), StackPtr)
+        .addReg(StackPtr)
+        .addImm(TailOffset)
         .setMIFlag(MachineInstr::FrameSetup);
   }
 
   // Update Live In information
   recomputeLiveIns(*testMBB);
   recomputeLiveIns(*tailMBB);
 }
 

llvm/lib/Target/X86/X86ISelLowering.cpp

BuildMI(*MBB, {MI}, DL, TII->get(Opc), FinalStackPtr)
         .addReg(TmpStackPtr)
         .addReg(sizeVReg);
   }
 
   // test rsp size
 
   BuildMI(testMBB, DL,
           TII->get(TFI.Uses64BitFramePtr ? X86::CMP64rr : X86::CMP32rr))
-      .addReg(physSPReg)
-      .addReg(FinalStackPtr);
+      .addReg(FinalStackPtr)
+      .addReg(physSPReg);
 
   BuildMI(testMBB, DL, TII->get(X86::JCC_1))
       .addMBB(tailMBB)
       .addImm(X86::COND_L);
   testMBB->addSuccessor(blockMBB);
   testMBB->addSuccessor(tailMBB);
 
   // Touch the block then extend it. This is done on the opposite side of

llvm/test/CodeGen/X86/stack-clash-dynamic-alloca.ll

 ; CHECK-X86-64-NEXT:    .cfi_offset %rbp, -16
 ; CHECK-X86-64-NEXT:    movq  %rsp, %rbp
 ; CHECK-X86-64-NEXT:    .cfi_def_cfa_register %rbp
 ; CHECK-X86-64-NEXT:    movq    %rsp, %rax
 ; CHECK-X86-64-NEXT:    movl    %edi, %ecx
 ; CHECK-X86-64-NEXT:    leaq 15(,%rcx,4), %rcx
 ; CHECK-X86-64-NEXT:    andq  $-16, %rcx
 ; CHECK-X86-64-NEXT:    subq  %rcx, %rax
-; CHECK-X86-64-NEXT:    cmpq  %rax, %rsp
+; CHECK-X86-64-NEXT:    cmpq  %rsp, %rax
 ; CHECK-X86-64-NEXT:    jl  .LBB0_3
 ; CHECK-X86-64-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1
 ; CHECK-X86-64-NEXT:    movq  $0, (%rsp)
 ; CHECK-X86-64-NEXT:    subq  $4096, %rsp # imm = 0x1000
-; CHECK-X86-64-NEXT:    cmpq  %rax, %rsp
+; CHECK-X86-64-NEXT:    cmpq  %rsp, %rax
 ; CHECK-X86-64-NEXT:    jge .LBB0_2
 ; CHECK-X86-64-NEXT:  .LBB0_3:
 ; CHECK-X86-64-NEXT:    movq  %rax, %rsp
 ; CHECK-X86-64-NEXT:    movl  $1, 4792(%rax)
 ; CHECK-X86-64-NEXT:    movl  (%rax), %eax
 ; CHECK-X86-64-NEXT:    movq  %rbp, %rsp
 ; CHECK-X86-64-NEXT:    popq  %rbp
 ; CHECK-X86-64-NEXT:  .cfi_def_cfa %rsp, 8
 ; CHECK-X86-64-NEXT:   retq
 
 
 ; CHECK-X86-32-LABEL: foo:
 ; CHECK-X86-32:       # %bb.0:
 ; CHECK-X86-32-NEXT:    pushl   %ebp
 ; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-X86-32-NEXT:    .cfi_offset %ebp, -8
 ; CHECK-X86-32-NEXT:    movl    %esp, %ebp
 ; CHECK-X86-32-NEXT:    .cfi_def_cfa_register %ebp
 ; CHECK-X86-32-NEXT:    subl    $8, %esp
 ; CHECK-X86-32-NEXT:    movl    8(%ebp), %ecx
 ; CHECK-X86-32-NEXT:    movl    %esp, %eax
 ; CHECK-X86-32-NEXT:    leal    15(,%ecx,4), %ecx
 ; CHECK-X86-32-NEXT:    andl    $-16, %ecx
 ; CHECK-X86-32-NEXT:    subl    %ecx, %eax
-; CHECK-X86-32-NEXT:    cmpl    %eax, %esp
+; CHECK-X86-32-NEXT:    cmpl    %esp, %eax
 ; CHECK-X86-32-NEXT:    jl  .LBB0_3
 ; CHECK-X86-32-NEXT:  .LBB0_2: # =>This Inner Loop Header: Depth=1
 ; CHECK-X86-32-NEXT:    movl    $0, (%esp)
 ; CHECK-X86-32-NEXT:    subl    $4096, %esp # imm = 0x1000
-; CHECK-X86-32-NEXT:    cmpl    %eax, %esp
+; CHECK-X86-32-NEXT:    cmpl    %esp, %eax
 ; CHECK-X86-32-NEXT:    jge .LBB0_2
 ; CHECK-X86-32-NEXT:  .LBB0_3:
 ; CHECK-X86-32-NEXT:    movl    %eax, %esp
 ; CHECK-X86-32-NEXT:    movl    $1, 4792(%eax)
 ; CHECK-X86-32-NEXT:    movl    (%eax), %eax
 ; CHECK-X86-32-NEXT:    movl    %ebp, %esp
 ; CHECK-X86-32-NEXT:    popl    %ebp
 ; CHECK-X86-32-NEXT:    .cfi_def_cfa %esp, 4
 ; CHECK-X86-32-NEXT:    retl
 

llvm/test/CodeGen/X86/stack-clash-large.ll

 
 ; CHECK-X86-64-LABEL: foo:
 ; CHECK-X86-64:        # %bb.0:
 ; CHECK-X86-64-NEXT:  movq  %rsp, %r11
 ; CHECK-X86-64-NEXT:  subq  $69632, %r11 # imm = 0x11000
 ; CHECK-X86-64-NEXT:   .LBB0_1:
 ; CHECK-X86-64-NEXT:  subq  $4096, %rsp # imm = 0x1000
 ; CHECK-X86-64-NEXT:  movq  $0, (%rsp)
 ; CHECK-X86-64-NEXT:  cmpq  %r11, %rsp
-; CHECK-X86-64-NEXT:  jl  .LBB0_1
+; CHECK-X86-64-NEXT:  jne .LBB0_1
 ; CHECK-X86-64-NEXT:# %bb.2:
-; CHECK-X86-64-NEXT:  movq    %r11, %rsp
+; CHECK-X86-64-NEXT:  subq    $2248, %rsp
 ; CHECK-X86-64-NEXT:  .cfi_def_cfa_offset 71888
 ; CHECK-X86-64-NEXT:  movl  $1, 264(%rsp)
 ; CHECK-X86-64-NEXT:  movl  $1, 28664(%rsp)
 ; CHECK-X86-64-NEXT:  movl  -128(%rsp), %eax
 ; CHECK-X86-64-NEXT:  addq  $71880, %rsp # imm = 0x118C8
 ; CHECK-X86-64-NEXT:  .cfi_def_cfa_offset 8
 ; CHECK-X86-64-NEXT:  retq
 
 ; CHECK-X86-32-LABEL: foo:
 ; CHECK-X86-32:      # %bb.0:
 ; CHECK-X86-32-NEXT:    movl    %esp, %r11d
 ; CHECK-X86-32-NEXT:    subl    $69632, %r11d # imm = 0x11000
 ; CHECK-X86-32-NEXT:    .LBB0_1: # =>This Inner Loop Header: Depth=1
 ; CHECK-X86-32-NEXT:    subl    $4096, %esp # imm = 0x1000
 ; CHECK-X86-32-NEXT:    movl    $0, (%esp)
 ; CHECK-X86-32-NEXT:    cmpl    %r11d, %esp
-; CHECK-X86-32-NEXT:    jl  .LBB0_1
+; CHECK-X86-32-NEXT:    jne  .LBB0_1
 ; CHECK-X86-32-NEXT:# %bb.2:
-; CHECK-X86-32-NEXT:    movl    %r11d, %esp
+; CHECK-X86-32-NEXT:    subl    $2380, %esp
 ; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 72016
 ; CHECK-X86-32-NEXT:    movl    $1, 392(%esp)
 ; CHECK-X86-32-NEXT:    movl    $1, 28792(%esp)
 ; CHECK-X86-32-NEXT:    movl    (%esp), %eax
 ; CHECK-X86-32-NEXT:    addl    $72012, %esp # imm = 0x1194C
 ; CHECK-X86-32-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-X86-32-NEXT:    retl