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[TargetLowering] Improve expansion of FSHL/FSHR by non-zero amount
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Authored by foad on Jun 25 2020, 3:57 AM.

Details

Summary

Use a simpler code sequence when the shift amount is known not to be
zero modulo the bit width.

Nothing much uses this until D77152 changes the translation of fshl and
fshr intrinsics.

Diff Detail

Event Timeline

foad created this revision.Jun 25 2020, 3:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 25 2020, 3:57 AM
arsenm added a subscriber: arsenm.Jul 3 2020, 10:33 AM
arsenm added inline comments.
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
6121

!isDivisibleByBitWidth()?

This revision was not accepted when it landed; it landed in state Needs Review.Jul 6 2020, 4:30 AM
This revision was automatically updated to reflect the committed changes.
foad marked an inline comment as done.
foad added inline comments.Jul 6 2020, 4:30 AM
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
6121

I don't think that's a good idea because it's a tri-state question: is Z known to be divisible by BW, or known to be non-zero mod BW, or unknown?

foad added a comment.Jul 7 2020, 12:34 AM

I misread something and thought @arsenm had accepted this patch. That's why I committed it.