[AMDGPU][CODEGEN] Added support for inline assembler constraints 'L' and 'Kf'

[dp]

Summary

Added support for constraints 'L', and 'Kf'. See https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints.

The purpose and usefulness of these constraints is not clear so integration of this change is postponed. See discussion in D81651.

llvm/docs/LangRef.rst

 AMDGPU:
 
 - ``r``: A 32 or 64-bit integer register.
 - ``[0-9]v``: The 32-bit VGPR register, number 0-9.
 - ``[0-9]s``: The 32-bit SGPR register, number 0-9.
 - ``[0-9]a``: The 32-bit AGPR register, number 0-9.
 - ``I``: An integer inline constant in the range from -16 to 64.
 - ``J``: A 16-bit signed integer constant.
+- ``L``: A 15-bit unsigned integer constant.
 - ``A``: An integer or a floating-point inline constant.
 - ``B``: A 32-bit signed integer constant.
 - ``C``: A 32-bit unsigned integer constant or an integer inline constant in the range from -16 to 64.
+- ``Kf``: An integer constant -1.
 - ``DA``: A 64-bit constant that can be split into two "A" constants.
 - ``DB``: A 64-bit constant that can be split into two "B" constants.
 
 All ARM modes:
 
 - ``Q``, ``Um``, ``Un``, ``Uq``, ``Us``, ``Ut``, ``Uv``, ``Uy``: Memory address
   operand. Treated the same as operand ``m``, at the moment.
 - ``Te``: An even general-purpose 32-bit integer register: ``r0,r2,...,r12,r14``

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 }
 
 static bool isImmConstraint(StringRef Constraint) {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     default: break;
     case 'I':
     case 'J':
+    case 'L':
     case 'A':
     case 'B':
     case 'C':
       return true;
     }
-  } else if (Constraint == "DA" ||
+  } else if (Constraint == "Kf" ||
+             Constraint == "DA" ||
              Constraint == "DB") {
     return true;
   }
   return false;
 }
 
 SITargetLowering::ConstraintType
 SITargetLowering::getConstraintType(StringRef Constraint) const {
bool SITargetLowering::checkAsmConstraintVal(SDValue Op,
                                              const std::string &Constraint,
                                              uint64_t Val) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'I':
       return AMDGPU::isInlinableIntLiteral(Val);
     case 'J':
       return isInt<16>(Val);
+    case 'L':
+      return isUInt<15>(Val);
     case 'A':
       return checkAsmConstraintValA(Op, Val);
     case 'B':
       return isInt<32>(Val);
     case 'C':
       return isUInt<32>(clearUnusedBits(Val, Op.getScalarValueSizeInBits())) ||
              AMDGPU::isInlinableIntLiteral(Val);
     default:
       break;
     }
   } else if (Constraint.size() == 2) {
+    if (Constraint == "Kf") {
+      return static_cast<int64_t>(Val) == -1;
+    }
     if (Constraint == "DA") {
       int64_t HiBits = static_cast<int32_t>(Val >> 32);
       int64_t LoBits = static_cast<int32_t>(Val);
       return checkAsmConstraintValA(Op, HiBits, 32) &&
              checkAsmConstraintValA(Op, LoBits, 32);
     }
     if (Constraint == "DB") {
       return true;

llvm/test/CodeGen/AMDGPU/inline-constraints.ll

 
 ; NOGCN: error: invalid operand for inline asm constraint 'J'
 define i32 @inline_J_constraint_E2() {
   %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,J"(i128 100000000000000000000)
   ret i32 %v0
 }
 
 ;==============================================================================
+; 'L' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'L'
+; VI-LABEL: {{^}}inline_L_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_L_constraint_H0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i16 32767)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'L'
+; VI-LABEL: {{^}}inline_L_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, 0
+define i32 @inline_L_constraint_H1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i16 0)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'L'
+; VI-LABEL: {{^}}inline_L_constraint_H3:
+; VI: v_mov_b32 {{v[0-9]+}}, 16
+define i32 @inline_L_constraint_H3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(half bitcast (i16 16 to half))
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_H8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i16 32768)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_H9() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i16 -1)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'L' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_L_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0
+define i32 @inline_L_constraint_F0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i32 0)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_L_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_L_constraint_F1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i32 32767)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_F2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i32 -1)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_F3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i32 32768)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_F4() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(float -4.0)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'L' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_L_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_L_constraint_D0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i64 32767)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_L_constraint_D1:
+; GCN: v_mov_b32 {{v[0-9]+}}, 0
+define i32 @inline_L_constraint_D1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i64 0)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_D8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i64 32768)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_D9() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(i64 -1)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'L' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'L'
+; VI-LABEL: {{^}}inline_L_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, 0
+define i32 @inline_L_constraint_V0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(<2 x i16> <i16 0, i16 0>)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'L'
+; VI-LABEL: {{^}}inline_L_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
+define i32 @inline_L_constraint_V1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(<2 x i16> <i16 32767, i16 32767>)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_V2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(<2 x i16> <i16 32768, i16 32768>)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'L'
+define i32 @inline_L_constraint_V3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,L"(<2 x i16> <i16 -1, i16 -1>)
+  ret i32 %v0
+}
+
+;==============================================================================
 ; 'B' constraint, 16-bit operand
 ;==============================================================================
 
 ; NOSI: error: invalid operand for inline asm constraint 'B'
 ; VI-LABEL: {{^}}inline_B_constraint_H0:
 ; VI: v_mov_b32 {{v[0-9]+}}, 0x7fff
 define i32 @inline_B_constraint_H0() {
   %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,B"(i16 32767)

 ; VI-LABEL: {{^}}inline_C_constraint_V2:
 ; VI: v_mov_b32 {{v[0-9]+}}, 0x8000
 define i32 @inline_C_constraint_V2() {
   %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,C"(<2 x i16> <i16 -32768, i16 -32768>)
   ret i32 %v0
 }
 
 ;==============================================================================
+; 'Kf' constraint, 16-bit operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'Kf'
+; VI-LABEL: {{^}}inline_Kf_constraint_H0:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_H0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i16 -1)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'Kf'
+; VI-LABEL: {{^}}inline_Kf_constraint_H1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_H1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i16 65535)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_H2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i16 -2)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_H3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i16 0)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_H4() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(half -1.0)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'Kf' constraint, 32-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_Kf_constraint_F0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_F0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i32 4294967295)
+  ret i32 %v0
+}
+
+; GCN-LABEL: {{^}}inline_Kf_constraint_F1:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_F1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i32 -1)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_F2() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i32 2147483648)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_F3() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i32 0)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_F4() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i32 -2)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_F5() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(float -1.0)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'Kf' constraint, 64-bit operand
+;==============================================================================
+
+; GCN-LABEL: {{^}}inline_Kf_constraint_D0:
+; GCN: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_D0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i64 -1)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_D6() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i64 4294967295)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_D7() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i64 2147483648)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_D8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i64 -2)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_D9() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(i64 0)
+  ret i32 %v0
+}
+
+;==============================================================================
+; 'Kf' constraint, v2x16 operand
+;==============================================================================
+
+; NOSI: error: invalid operand for inline asm constraint 'Kf'
+; VI-LABEL: {{^}}inline_Kf_constraint_V0:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_V0() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(<2 x i16> <i16 65535, i16 65535>)
+  ret i32 %v0
+}
+
+; NOSI: error: invalid operand for inline asm constraint 'Kf'
+; VI-LABEL: {{^}}inline_Kf_constraint_V1:
+; VI: v_mov_b32 {{v[0-9]+}}, -1
+define i32 @inline_Kf_constraint_V1() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(<2 x i16> <i16 -1, i16 -1>)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_V8() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(<2 x i16> <i16 -2, i16 -2>)
+  ret i32 %v0
+}
+
+; NOGCN: error: invalid operand for inline asm constraint 'Kf'
+define i32 @inline_Kf_constraint_V9() {
+  %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^Kf"(<2 x i16> <i16 0, i16 0>)
+  ret i32 %v0
+}
+
+;==============================================================================
 ; 'DA' constraint, 16-bit operand
 ;==============================================================================
 
 ; NOSI: error: invalid operand for inline asm constraint 'DA'
 ; VI-LABEL: {{^}}inline_DA_constraint_H0:
 ; VI: v_mov_b32 {{v[0-9]+}}, 64
 define i32 @inline_DA_constraint_H0() {
   %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,^DA"(i16 64)