[NFC] Remove assert from SelectionDAG::getZeroExtendInReg

[paquette]

Summary

Remove the assert from SelectionDAG::getZeroExtendInReg which checks that OpVT.isVector() == VT.isVector().

This assert was added in c41685b16fcceaa2078eb14eb27f6696f851eb49. This did some refactoring to reduce the number of calls to getScalarType.

If you're building stuff for arm64_32, it's possible to break this assumption.

E.g. in SelectionDAGBuilder::visitGetElementPtr:

MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS);
MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS);
...
if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds())
  N = DAG.getPtrExtendInReg(N, dl, PtrMemTy);

All getPtrExtendInReg does is return getZeroExtendInReg. So, if N is a vector, we'll hit the assert.

Add a testcase to arm64_32-pointer-extend.ll that shows an example of this.

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

1177

This bitLE check doesn't check what its intending to check if VT is a scalar and OpVT is a vector. Should probably check the bits of the scalar type.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT,
   TargetLowering::BooleanContent BType = TLI->getBooleanContents(OpVT);
   return getNode(TLI->getExtendForContent(BType), SL, VT, Op);
 }
 
 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) {
   EVT OpVT = Op.getValueType();
   assert(VT.isInteger() && OpVT.isInteger() &&
          "Cannot getZeroExtendInReg FP types");
-  assert(VT.isVector() == OpVT.isVector() &&
-         "getZeroExtendInReg type should be vector iff the operand "
-         "type is vector!");
   assert((!VT.isVector() ||
           VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
          "Vector element counts must match in getZeroExtendInReg");
   assert(VT.bitsLE(OpVT) && "Not extending!");
   if (OpVT == VT)
     return Op;
   APInt Imm = APInt::getLowBitsSet(OpVT.getScalarSizeInBits(),
                                    VT.getScalarSizeInBits());
   return getNode(ISD::AND, DL, OpVT, Op, getConstant(Imm, DL, OpVT));
 }
 
 SDValue SelectionDAG::getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {

llvm/test/CodeGen/AArch64/arm64_32-pointer-extend.ll

 ; CHECK: sdiv [[VAL64:x[0-9]+]], x0, x1
 ; CHECK: and x0, [[VAL64]], #0xffffffff
 
   %sum = sdiv i64 %in, %r
   %sum32 = trunc i64 %sum to i32
   %res = inttoptr i32 %sum32 to i8*
   ret i8* %res
 }
+
+define <2 x i8*> @gep_with_vector() {
+; CHECK-LABEL: gep_with_vector:
+; CHECK: movi.2d  v0, #0000000000000000
+; CHECK-NEXT: ret
+  %vec = getelementptr i8, <2 x i8*> undef, <2 x i32> <i32 42, i32 42>
+  ret <2 x i8*> %vec
+}