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Differential D81971

[AVR] Disassemble multiplication instructions
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Authored by aykevl on Jun 16 2020, 2:50 PM.

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Reviewers
dylanmckay
Commits
rGec9efb856c6f: [AVR] Disassemble multiplication instructions
Summary

These can often only use a limited range of registers, and apparently need special decoding support.

Diff Detail

Event Timeline

aykevl created this revision.Jun 16 2020, 2:50 PM
Herald added subscribers: Jim, hiraditya. · View Herald TranscriptJun 16 2020, 2:50 PM
Harbormaster failed remote builds in B60550: Diff 271214!Jun 16 2020, 2:56 PM
dylanmckay requested changes to this revision.Jun 17 2020, 10:55 PM

Couple of nitpicks, otherwise good to go.

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
174

Fit to 80 characters, prefer return on a new line

183

Same here re. 80 chars

This revision now requires changes to proceed.Jun 17 2020, 10:55 PM
aykevl updated this revision to Diff 271646.Jun 18 2020, 3:33 AM
  • fix formatting
Harbormaster failed remote builds in B60795: Diff 271646!Jun 18 2020, 4:19 AM
dylanmckay accepted this revision.Jun 18 2020, 10:13 PM
This revision is now accepted and ready to land.Jun 18 2020, 10:13 PM
Closed by commit rGec9efb856c6f: [AVR] Disassemble multiplication instructions (authored by aykevl). · Explain WhyJun 22 2020, 5:45 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AVR/
4 lines
Disassembler/
28 lines
test/
MC/
AVR/
12 lines
6 lines
6 lines
12 lines
6 lines

Diff 271646

llvm/lib/Target/AVR/AVRInstrFormats.td

Show First 20 Lines • Show All 266 Lines • ▼ Show 20 Lines
{ {
bits<5> rd; // accept 5 bits but only encode the lower 4 bits<5> rd; // accept 5 bits but only encode the lower 4
bits<5> rr; // accept 5 bits but only encode the lower 4 bits<5> rr; // accept 5 bits but only encode the lower 4
let Inst{15-9} = 0b0000001; let Inst{15-9} = 0b0000001;
let Inst{8} = f; let Inst{8} = f;
let Inst{7-4} = rd{3-0}; let Inst{7-4} = rd{3-0};
let Inst{3-0} = rr{3-0}; let Inst{3-0} = rr{3-0};
let DecoderMethod = "decodeFMUL2RdRr";
} }
// Special encoding for the FMUL family of instructions. // Special encoding for the FMUL family of instructions.
// //
// <0000|0011|fddd|frrr|> // <0000|0011|fddd|frrr|>
// //
// ff = 0b01 for FMUL // ff = 0b01 for FMUL
// 0b10 for FMULS // 0b10 for FMULS
// 0b11 for FMULSU // 0b11 for FMULSU
// //
// ddd = destination register // ddd = destination register
// rrr = source register // rrr = source register
class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern> class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> : AVRInst16<outs, ins, asmstr, pattern>
{ {
bits<3> rd; bits<3> rd;
bits<3> rr; bits<3> rr;
let Inst{15-8} = 0b00000011; let Inst{15-8} = 0b00000011;
let Inst{7} = f{1}; let Inst{7} = f{1};
let Inst{6-4} = rd; let Inst{6-4} = rd;
let Inst{3} = f{0}; let Inst{3} = f{0};
let Inst{2-0} = rr; let Inst{2-0} = rr;
let DecoderMethod = "decodeFFMULRdRr";
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|> // Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
// f = secondary opcode = 1 bit // f = secondary opcode = 1 bit
// k = constant data = 6 bits // k = constant data = 6 bits
// d = destination = 4 bits // d = destination = 4 bits
▲ Show 20 Lines • Show All 281 Lines • Show Last 20 Lines

llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Linesstatic DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn, static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder); uint64_t Address, const void *Decoder);
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
#include "AVRGenDisassemblerTables.inc" #include "AVRGenDisassemblerTables.inc"
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned addr = 0; unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4); addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4; addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5); unsigned reg = fieldFromInstruction(Insn, 4, 5);
Show All 35 Lines
static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) { uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 5); unsigned d = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail) if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail; return MCDisassembler::Fail;
return MCDisassembler::Success; return MCDisassembler::Success;
} }
static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 3) + 16;
unsigned r = fieldFromInstruction(Insn, 0, 3) + 16;
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) == MCDisassembler::Fail)
dylanmckayUnsubmitted
Not Done
ReplyInline Actions

Fit to 80 characters, prefer return on a new line

dylanmckay: Fit to 80 characters, prefer `return` on a new line
return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
unsigned rd = fieldFromInstruction(Insn, 4, 4) + 16;
dylanmckayUnsubmitted
Not Done
ReplyInline Actions

Same here re. 80 chars

dylanmckay: Same here re. 80 chars
unsigned rr = fieldFromInstruction(Insn, 0, 4) + 16;
if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) == MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}
static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
uint64_t &Size, uint32_t &Insn) { uint64_t &Size, uint32_t &Insn) {
if (Bytes.size() < 2) { if (Bytes.size() < 2) {
Size = 0; Size = 0;
return MCDisassembler::Fail; return MCDisassembler::Fail;
} }
Size = 2; Size = 2;
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

llvm/test/MC/AVR/inst-fmul.s

; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s | llvm-objdump -d --mattr=mul - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
fmul r22, r16 fmul r22, r16
fmul r19, r17 fmul r19, r17
fmul r21, r23 fmul r21, r23
fmul r23, r23 fmul r23, r23
fmul r16, r16
fmul r16, r23
; CHECK: fmul r22, r16 ; encoding: [0x68,0x03] ; CHECK: fmul r22, r16 ; encoding: [0x68,0x03]
; CHECK: fmul r19, r17 ; encoding: [0x39,0x03] ; CHECK: fmul r19, r17 ; encoding: [0x39,0x03]
; CHECK: fmul r21, r23 ; encoding: [0x5f,0x03] ; CHECK: fmul r21, r23 ; encoding: [0x5f,0x03]
; CHECK: fmul r23, r23 ; encoding: [0x7f,0x03] ; CHECK: fmul r23, r23 ; encoding: [0x7f,0x03]
; CHECK: fmul r16, r16 ; encoding: [0x08,0x03]
; CHECK: fmul r16, r23 ; encoding: [0x0f,0x03]
; CHECK-INST: fmul r22, r16
; CHECK-INST: fmul r19, r17
; CHECK-INST: fmul r21, r23
; CHECK-INST: fmul r23, r23
; CHECK-INST: fmul r16, r16
; CHECK-INST: fmul r16, r23

llvm/test/MC/AVR/inst-fmuls.s

; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s | llvm-objdump -d --mattr=mul - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
fmuls r22, r16 fmuls r22, r16
fmuls r19, r17 fmuls r19, r17
fmuls r21, r23 fmuls r21, r23
fmuls r23, r23 fmuls r23, r23
; CHECK: fmuls r22, r16 ; encoding: [0xe0,0x03] ; CHECK: fmuls r22, r16 ; encoding: [0xe0,0x03]
; CHECK: fmuls r19, r17 ; encoding: [0xb1,0x03] ; CHECK: fmuls r19, r17 ; encoding: [0xb1,0x03]
; CHECK: fmuls r21, r23 ; encoding: [0xd7,0x03] ; CHECK: fmuls r21, r23 ; encoding: [0xd7,0x03]
; CHECK: fmuls r23, r23 ; encoding: [0xf7,0x03] ; CHECK: fmuls r23, r23 ; encoding: [0xf7,0x03]
; CHECK-INST: fmuls r22, r16
; CHECK-INST: fmuls r19, r17
; CHECK-INST: fmuls r21, r23
; CHECK-INST: fmuls r23, r23

llvm/test/MC/AVR/inst-fmulsu.s

; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s | llvm-objdump -d --mattr=mul - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
fmulsu r22, r16 fmulsu r22, r16
fmulsu r19, r17 fmulsu r19, r17
fmulsu r21, r23 fmulsu r21, r23
fmulsu r23, r23 fmulsu r23, r23
; CHECK: fmulsu r22, r16 ; encoding: [0xe8,0x03] ; CHECK: fmulsu r22, r16 ; encoding: [0xe8,0x03]
; CHECK: fmulsu r19, r17 ; encoding: [0xb9,0x03] ; CHECK: fmulsu r19, r17 ; encoding: [0xb9,0x03]
; CHECK: fmulsu r21, r23 ; encoding: [0xdf,0x03] ; CHECK: fmulsu r21, r23 ; encoding: [0xdf,0x03]
; CHECK: fmulsu r23, r23 ; encoding: [0xff,0x03] ; CHECK: fmulsu r23, r23 ; encoding: [0xff,0x03]
; CHECK-INST: fmulsu r22, r16
; CHECK-INST: fmulsu r19, r17
; CHECK-INST: fmulsu r21, r23
; CHECK-INST: fmulsu r23, r23

llvm/test/MC/AVR/inst-muls.s

; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s | llvm-objdump -d --mattr=mul - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
muls r22, r16 muls r22, r16
muls r19, r17 muls r19, r17
muls r28, r31 muls r28, r31
muls r31, r31 muls r31, r31
muls r16, r16
muls r16, r31
; CHECK: muls r22, r16 ; encoding: [0x60,0x02] ; CHECK: muls r22, r16 ; encoding: [0x60,0x02]
; CHECK: muls r19, r17 ; encoding: [0x31,0x02] ; CHECK: muls r19, r17 ; encoding: [0x31,0x02]
; CHECK: muls r28, r31 ; encoding: [0xcf,0x02] ; CHECK: muls r28, r31 ; encoding: [0xcf,0x02]
; CHECK: muls r31, r31 ; encoding: [0xff,0x02] ; CHECK: muls r31, r31 ; encoding: [0xff,0x02]
; CHECK: muls r16, r16 ; encoding: [0x00,0x02]
; CHECK: muls r16, r31 ; encoding: [0x0f,0x02]
; CHECK-INST: muls r22, r16
; CHECK-INST: muls r19, r17
; CHECK-INST: muls r28, r31
; CHECK-INST: muls r31, r31
; CHECK-INST: muls r16, r16
; CHECK-INST: muls r16, r31

llvm/test/MC/AVR/inst-mulsu.s

; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s ; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s | llvm-objdump -d --mattr=mul - | FileCheck -check-prefix=CHECK-INST %s
foo: foo:
mulsu r22, r16 mulsu r22, r16
mulsu r19, r17 mulsu r19, r17
mulsu r21, r23 mulsu r21, r23
mulsu r23, r23 mulsu r23, r23
; CHECK: mulsu r22, r16 ; encoding: [0x60,0x03] ; CHECK: mulsu r22, r16 ; encoding: [0x60,0x03]
; CHECK: mulsu r19, r17 ; encoding: [0x31,0x03] ; CHECK: mulsu r19, r17 ; encoding: [0x31,0x03]
; CHECK: mulsu r21, r23 ; encoding: [0x57,0x03] ; CHECK: mulsu r21, r23 ; encoding: [0x57,0x03]
; CHECK: mulsu r23, r23 ; encoding: [0x77,0x03] ; CHECK: mulsu r23, r23 ; encoding: [0x77,0x03]
; CHECK-INST: mulsu r22, r16
; CHECK-INST: mulsu r19, r17
; CHECK-INST: mulsu r21, r23
; CHECK-INST: mulsu r23, r23