Fix ubsan error in tblgen with signed left shift

[rampitec]

Summary

UBSAN complains when tblgen performs SHL of a negative
value.

llvm/lib/TableGen/Record.cpp

if (LHSi && RHSi) {
       int64_t LHSv = LHSi->getValue(), RHSv = RHSi->getValue();
       int64_t Result;
       switch (getOpcode()) {
       default: llvm_unreachable("Bad opcode!");
       case ADD: Result = LHSv +  RHSv; break;
       case MUL: Result = LHSv *  RHSv; break;
       case AND: Result = LHSv &  RHSv; break;
       case OR: Result = LHSv | RHSv; break;
-      case SHL: Result = LHSv << RHSv; break;
+      case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break;
       case SRA: Result = LHSv >> RHSv; break;
       case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
       }
       return IntInit::get(Result);
     }
     break;
   }
   }

llvm/lib/Target/AMDGPU/SMInstructions.td

def : GCNPat <
   (S_MEMTIME)
 >;
 } // let OtherPredicates = [HasSMemTimeInst]
 
 let OtherPredicates = [HasNoSMemTimeInst] in {
 def : GCNPat <
   (i64 (readcyclecounter)),
   (REG_SEQUENCE SReg_64,
-    (S_GETREG_B32 -26595), sub0,
+    (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
     (S_MOV_B32 (i32 0)), sub1)
 >;
 } // let OtherPredicates = [HasNoSMemTimeInst]
 
 //===----------------------------------------------------------------------===//
 // GFX10.
 //===----------------------------------------------------------------------===//