[aarch64] Distinguish the 'Q' and 'm' inline assembly memory constraints.

[dsanders]

Summary

But still handle them the same way since I don't know how they differ on
this target.

Clang also has code for 'Ump', 'Utf', 'Usa', and 'Ush' but calls
llvm_unreachable() on this code path so they have are not converted to a
constraint id at the moment.

No functional change intended. Depends on D8173.

[dsanders]

Ping.

The main thing I'm looking for is for is for someone with knowledge of the target to say whether they're aware of any supported constraints that this patch doesn't cover.

[t.p.northover]

Hi Daniel,

[dsanders]

Thanks. Committed in r232941.

llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
                                   uint64_t &Imm) {
   return N->getOpcode() == Opc &&
          isIntImmediate(N->getOperand(1).getNode(), Imm);
 }
 
 bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
-  assert(ConstraintID == InlineAsm::Constraint_m &&
-         "unexpected asm memory constraint");
+  switch(ConstraintID) {
+  default:
+    llvm_unreachable("Unexpected asm memory constraint");
+  case InlineAsm::Constraint_i:
+  case InlineAsm::Constraint_m:
+  case InlineAsm::Constraint_Q:
     // Require the address to be in a register.  That is safe for all AArch64
     // variants and it is hard to do anything much smarter without knowing
     // how the operand is used.
     OutOps.push_back(Op);
     return false;
   }
+  return true;
+}
 
 /// SelectArithImmed - Select an immediate value that can be represented as
 /// a 12-bit value shifted left by either 0 or 12.  If so, return true with
 /// Val set to the 12-bit value and Shift set to the shifter operand.
 bool AArch64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
                                            SDValue &Shift) {
   // This function is called from the addsub_shifted_imm ComplexPattern,
   // which lists [imm] as the list of opcode it's interested in, however

llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.h

getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                const std::string &Constraint,
                                MVT VT) const override;
   void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
   unsigned getInlineAsmMemConstraint(
       const std::string &ConstraintCode) const override {
-    // FIXME: Map different constraints differently.
-    return InlineAsm::Constraint_m;
+    if (ConstraintCode == "Q")
+      return InlineAsm::Constraint_Q;
+    // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
+    //        followed by llvm_unreachable so we'll leave them unimplemented in
+    //        the backend for now.
+    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
   }
 
   bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
   bool mayBeEmittedAsTailCall(CallInst *CI) const override;
   bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
                               ISD::MemIndexedMode &AM, bool &IsInc,
                               SelectionDAG &DAG) const;
   bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,