[x86] Distinguish the 'o', 'v', 'X', and 'i' inline assembly memory constraints.

[dsanders]

Summary

But still handle them the same way since I don't know how they differ on
this target.

Of these, 'o' and 'v' are not tested but were already implemented.

I'm not sure why 'i' is required for X86 since it's supposed to be an
immediate constraint rather than a memory constraint. A test asserts
without it so I've included it for now.

No functional change intended. Depends on D8173.

[dsanders]

Ping. The main thing I'm looking for is for is for someone with knowledge of the target to say whether they're aware of any supported constraints that this patch doesn't cover.

Chris: I've CC'd you since Nadav suggested I CC the original author of the code and I found that (cosmetic changes aside) it was added by you way back in r28728 (which was in 2006).

[dsanders]

Ping 2...

Nadav: I'm not sure there's anyone to review this patch. I'm pretty confident that I've got support for everything that was supported before but if there are any issues then it's going to be a simple matter of adding a case label and maybe a mapping from the constraint code to the constraint id. Would you be happy for me to commit if I agree to restore 'm' behaviour for any constraints that we find have somehow been missed out?

[dsanders]

Ping 3...

[dsanders]

Just to record it in phabricator. Nadav has replied and was ok with committing this patch. I'll commit in the morning

llvm/trunk/include/llvm/IR/InlineAsm.h

enum : uint32_t {
     Constraint_i,
     Constraint_m,
     Constraint_o,
     Constraint_v,
     Constraint_Q,
     Constraint_R,
     Constraint_S,
     Constraint_T,
+    Constraint_X,
     Constraint_Z,
     Constraint_ZC,
     Constraint_Zy,
     Constraints_Max = Constraint_Zy,
     Constraints_ShiftAmount = 16,
 
     Flag_MatchingOperand = 0x80000000
   };

llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp

SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
   return ResNode;
 }
 
 bool X86DAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
   SDValue Op0, Op1, Op2, Op3, Op4;
   switch (ConstraintID) {
+  default:
+    llvm_unreachable("Unexpected asm memory constraint");
+  case InlineAsm::Constraint_i:
+    // FIXME: It seems strange that 'i' is needed here since it's supposed to
+    //        be an immediate and not a memory constraint.
+    // Fallthrough.
   case InlineAsm::Constraint_o: // offsetable        ??
   case InlineAsm::Constraint_v: // not offsetable    ??
-  default: return true;
   case InlineAsm::Constraint_m: // memory
+  case InlineAsm::Constraint_X:
     if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   OutOps.push_back(Op2);

llvm/trunk/lib/Target/X86/X86ISelLowering.h

public:
     /// constraint of the inline asm instruction being processed is 'm'.
     void LowerAsmOperandForConstraint(SDValue Op,
                                       std::string &Constraint,
                                       std::vector<SDValue> &Ops,
                                       SelectionDAG &DAG) const override;
 
     unsigned getInlineAsmMemConstraint(
         const std::string &ConstraintCode) const override {
-      // FIXME: Map different constraints differently.
-      return InlineAsm::Constraint_m;
+      if (ConstraintCode == "i")
+        return InlineAsm::Constraint_i;
+      else if (ConstraintCode == "o")
+        return InlineAsm::Constraint_o;
+      else if (ConstraintCode == "v")
+        return InlineAsm::Constraint_v;
+      else if (ConstraintCode == "X")
+        return InlineAsm::Constraint_X;
+      return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
     }
 
     /// Given a physical register constraint
     /// (e.g. {edx}), return the register number and the register class for the
     /// register.  This should only be used for C_Register constraints.  On
     /// error, this returns a register number of 0.
     std::pair<unsigned, const TargetRegisterClass *>
     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,