[systemz] Distinguish the 'Q', 'R', 'S', and 'T' inline assembly memory constraints.

[dsanders]

Summary

But still handle them the same way since I don't know how they differ on
this target.

No functional change intended. Depends on D8173.

[uweigand]

LGTM. I'll change the actual behavior once this is in ...

include/llvm/IR/InlineAsm.h

enum : uint32_t {
     // there's plenty of space in the encoding to support the union of all
     // constraint codes for all targets.
     Constraint_Unknown = 0,
     Constraint_es,
     Constraint_m,
     Constraint_o,
     Constraint_v,
     Constraint_Q,
+    Constraint_R,
+    Constraint_S,
+    Constraint_T,
     Constraint_Um,
     Constraint_Un,
     Constraint_Uq,
     Constraint_Us,
     Constraint_Ut,
     Constraint_Uv,
     Constraint_Uy,
     Constraint_Z,

lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

DEBUG(errs() << "=> ";
         );
   return ResNode;
 }
 
 bool SystemZDAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op,
                              unsigned ConstraintID,
                              std::vector<SDValue> &OutOps) {
-  assert(ConstraintID == InlineAsm::Constraint_m &&
-         "Unexpected constraint code");
+  switch(ConstraintID) {
+  default:
+    llvm_unreachable("Unexpected asm memory constraint");
+  case InlineAsm::Constraint_m:
+  case InlineAsm::Constraint_Q:
+  case InlineAsm::Constraint_R:
+  case InlineAsm::Constraint_S:
+  case InlineAsm::Constraint_T:
     // Accept addresses with short displacements, which are compatible
     // with Q, R, S and T.  But keep the index operand for future expansion.
     SDValue Base, Disp, Index;
-  if (!selectBDXAddr(SystemZAddressingMode::FormBD,
+    if (selectBDXAddr(SystemZAddressingMode::FormBD,
                       SystemZAddressingMode::Disp12Only,
-                     Op, Base, Disp, Index))
-    return true;
+                      Op, Base, Disp, Index)) {
       OutOps.push_back(Base);
       OutOps.push_back(Disp);
       OutOps.push_back(Index);
       return false;
     }
+    break;
+  }
+  return true;
+}

lib/Target/SystemZ/SystemZISelLowering.h

getSingleConstraintMatchWeight(AsmOperandInfo &info,
                                    const char *constraint) const override;
   void LowerAsmOperandForConstraint(SDValue Op,
                                     std::string &Constraint,
                                     std::vector<SDValue> &Ops,
                                     SelectionDAG &DAG) const override;
 
   unsigned getInlineAsmMemConstraint(
       const std::string ConstraintCode) const override {
-    // FIXME: Map different constraints differently.
-    return InlineAsm::Constraint_m;
+    if (ConstraintCode.size() == 1) {
+      switch(ConstraintCode[0]) {
+      default:
+        break;
+      case 'Q':
+        return InlineAsm::Constraint_Q;
+      case 'R':
+        return InlineAsm::Constraint_R;
+      case 'S':
+        return InlineAsm::Constraint_S;
+      case 'T':
+        return InlineAsm::Constraint_T;
+      }
+    }
+    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
   }
 
   MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
                                                  MachineBasicBlock *BB) const
     override;
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
   bool allowTruncateForTailCall(Type *, Type *) const override;
   bool mayBeEmittedAsTailCall(CallInst *CI) const override;