[X86] Return 0 from TTI getNumberOfRegisters and getRegisterBitWidth on SSE1 only targets

[craig.topper]

Summary

SSE1 only supports vectors of v4f32. We're pretty much dependent on cost model calculations to prevent vectors of doubles or integers being generated. Or we rely on the backend scalarizing them. Even with that I'm not that confident in our SSE1 codegen quality.

We found a failure where the vectorizer was generating a call to a v4f64 SVML function with SSE1 only. This resulted in argument handling in the backend breaking the type down into scalars. Disabling SSE1 here prevents part of that although it still doesn't stop the vectorizer from generating the v4f64 call with SSE2

[spatel]

Add a minimal test for SLP to make sure this is happening? Might be able to just add a RUN line to some existing test file.

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

121

I'd word this differently to make it clearer:

// Avoid auto-vectorizing when compiling for SSE1 only. 
// That forces codegen to undo integer and v2f64 vectorization.

[craig.topper]

Add SSE1 command line to an SLP test.

[RKSimon]

Ideally getRegisterBitWidth/getNumberOfRegisters would distinguish between (legal) integer/float/double types more.

Have you made any progress on the SVML v4f64 SSE2 issue? I'm just wondering if that would avoid us needing to kill SSE1 vectorization entirely (although I realise its not a high priority target these days).

llvm/lib/Target/X86/X86TargetTransformInfo.cpp

case TargetTransformInfo::CacheLevel::L2D:
     return 8;
   }
 
   llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
 }
 
 unsigned X86TTIImpl::getNumberOfRegisters(unsigned ClassID) const {
   bool Vector = (ClassID == 1);
-  if (Vector && !ST->hasSSE1())
+  // SSE2 is required for integer vectors limiting usefulness with SSE1.
+  if (Vector && !ST->hasSSE2())
     return 0;
 
   if (ST->is64Bit()) {
     if (Vector && ST->hasAVX512())
       return 32;
     return 16;
   }
   return 8;
 }
 
 unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) const {
   unsigned PreferVectorWidth = ST->getPreferVectorWidth();
   if (Vector) {
     if (ST->hasAVX512() && PreferVectorWidth >= 512)
       return 512;
     if (ST->hasAVX() && PreferVectorWidth >= 256)
       return 256;
-    if (ST->hasSSE1() && PreferVectorWidth >= 128)
+    // SSE2 is required for integer vectors limiting usefulness of SSE1.
+    if (ST->hasSSE2() && PreferVectorWidth >= 128)
       return 128;
     return 0;
   }
 
   if (ST->is64Bit())
     return 64;
 
   return 32;