[PowerPC] fix a bug for folding RLWINM(LI) to LI due to wrap mask

[shchenz]

Summary

This is found during code review for https://reviews.llvm.org/D80907

See comment https://reviews.llvm.org/D80907#2068594

Peephole pass will convert following pattern:

%1:gprc = LI 100
%2:gprc = RLWINM %1:gprc, 1, 3, 2

to

%2:gprc = LI 0

The wrap mask is not handled well in convertToImmediateForm

[shchenz]

update test case

[steven.zhang]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3424

Can we fix this in the wrap？It does nothing now if lo == hi. But as it is [lo,hi), if lo == hi, we expect it to be all ones if it is with wrap.

[shchenz]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3424

Yeah, Good idea. We should differentiate getBitsSetWithWrap & getBitsSet when lo == hi. I will post a APInt patch soon to improve this.

[shchenz]

rebase based on https://reviews.llvm.org/D81325

[steven.zhang]

LGTM. Thank you for addressing this.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
   case PPC::RLWINM8:
   case PPC::RLWINM_rec:
   case PPC::RLWINM8_rec: {
     int64_t SH = MI.getOperand(2).getImm();
     int64_t MB = MI.getOperand(3).getImm();
     int64_t ME = MI.getOperand(4).getImm();
     APInt InVal(32, SExtImm, true);
     InVal = InVal.rotl(SH);
-    // Set the bits (        MB + 32        ) to (        ME + 32        ).
-    uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
+    APInt Mask = APInt::getBitsSetWithWrap(32, 32 - ME - 1, 32 - MB);
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use
     // ANDI_rec which won't sign extend, so that's safe.
     bool ValueFits = isUInt<15>(InVal.getSExtValue());
     ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) &&
                   isUInt<16>(InVal.getSExtValue()));
     if (ValueFits) {

llvm/test/CodeGen/PowerPC/fold-rlwinm.mir

bb.0.entry:
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 20, 5, 31
     ; CHECK: %2:gprc = RLWINM %1, 20, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 10, 20
     ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+name: testFoldRLWINMLIWrapMask
+#CHECK: name: testFoldRLWINMLIWrapMask
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    %0:gprc = COPY $x3
+    %1:gprc = LI 100
+    ; CHECK: %2:gprc = LI 200
+    %2:gprc = RLWINM %1:gprc, 1, 3, 2
+    STW %2:gprc, %0:gprc, 100
+    BLR8 implicit $lr8, implicit $rm
+...