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Differential D80920

AMDGPU: Fix alignment for dynamic allocas
ClosedPublic

Authored by arsenm on Jun 1 2020, 6:13 AM.

Details

Reviewers
scott.linder
rampitec
Summary

The alignment value also needs to be scaled by the wave size.

Diff Detail

Event Timeline

arsenm created this revision.Jun 1 2020, 6:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 1 2020, 6:13 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 7 others. · View Herald Transcript
madhur13490 added a subscriber: madhur13490.Jun 1 2020, 8:08 AM
madhur13490 added inline comments.
llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
98

Why is the opcode changed in assembly? you seemed to keep same DAG Opcode.

arsenm marked an inline comment as done.Jun 1 2020, 8:17 AM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
98

The inverted constant isn't an inline immediate so it wouldn't be beneficial to change it

rampitec accepted this revision.Jun 1 2020, 9:38 AM
This revision is now accepted and ready to land.Jun 1 2020, 9:38 AM
arsenm closed this revision.Jun 1 2020, 10:07 AM

7ad36491cadee1ed91e18215c30328a3d5c104f9

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
10 lines
test/
CodeGen/
AMDGPU/
4 lines

Diff 267593

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,120 Lines • ▼ Show 20 Lines unsigned Opc =
ISD::ADD : ISD::SUB; ISD::ADD : ISD::SUB;
SDValue ScaledSize = DAG.getNode( SDValue ScaledSize = DAG.getNode(
ISD::SHL, dl, VT, Size, ISD::SHL, dl, VT, Size,
DAG.getConstant(ST.getWavefrontSizeLog2(), dl, MVT::i32)); DAG.getConstant(ST.getWavefrontSizeLog2(), dl, MVT::i32));
unsigned StackAlign = TFL->getStackAlignment(); unsigned StackAlign = TFL->getStackAlignment();
Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
if (Align > StackAlign) if (Align > StackAlign) {
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1, Tmp1 = DAG.getNode(
DAG.getConstant(-(uint64_t)Align, dl, VT)); ISD::AND, dl, VT, Tmp1,
DAG.getConstant(-(uint64_t)Align << ST.getWavefrontSizeLog2(), dl, VT));
}
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
Tmp2 = DAG.getCALLSEQ_END( Tmp2 = DAG.getCALLSEQ_END(
Chain, DAG.getIntPtrConstant(0, dl, true), Chain, DAG.getIntPtrConstant(0, dl, true),
DAG.getIntPtrConstant(0, dl, true), SDValue(), dl); DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
return DAG.getMergeValues({Tmp1, Tmp2}, dl); return DAG.getMergeValues({Tmp1, Tmp2}, dl);
} }
▲ Show 20 Lines • Show All 8,310 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_add_u32 s0, s0, s9 ; GCN-NEXT: s_add_u32 s0, s0, s9
; GCN-NEXT: s_addc_u32 s1, s1, 0 ; GCN-NEXT: s_addc_u32 s1, s1, 0
; GCN-NEXT: s_mov_b32 s33, 0 ; GCN-NEXT: s_mov_b32 s33, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_cmp_lg_u32 s6, 0
; GCN-NEXT: s_cbranch_scc1 BB1_2 ; GCN-NEXT: s_cbranch_scc1 BB1_2
; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_add_i32 s6, s32, 0x1000 ; GCN-NEXT: s_add_i32 s6, s32, 0x1000
; GCN-NEXT: s_andn2_b32 s6, s6, 63 ; GCN-NEXT: s_and_b32 s6, s6, 0xfffff000
madhur13490Unsubmitted
Not Done
ReplyInline Actions

Why is the opcode changed in assembly? you seemed to keep same DAG Opcode.

madhur13490: Why is the opcode changed in assembly? you seemed to keep same DAG Opcode.
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

The inverted constant isn't an inline immediate so it wouldn't be beneficial to change it

arsenm: The inverted constant isn't an inline immediate so it wouldn't be beneficial to change it
; GCN-NEXT: s_lshl_b32 s7, s7, 2 ; GCN-NEXT: s_lshl_b32 s7, s7, 2
; GCN-NEXT: s_mov_b32 s32, s6 ; GCN-NEXT: s_mov_b32 s32, s6
; GCN-NEXT: v_mov_b32_e32 v2, s6 ; GCN-NEXT: v_mov_b32_e32 v2, s6
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_add_i32 s6, s6, s7 ; GCN-NEXT: s_add_i32 s6, s6, s7
; GCN-NEXT: v_mov_b32_e32 v3, 1 ; GCN-NEXT: v_mov_b32_e32 v3, 1
; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen offset:4
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b32 s7, s33 ; GCN-NEXT: s_mov_b32 s7, s33
; GCN-NEXT: s_and_b32 s33, s4, 0xfffff000 ; GCN-NEXT: s_and_b32 s33, s4, 0xfffff000
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GCN-NEXT: s_add_u32 s32, s32, 0x2000 ; GCN-NEXT: s_add_u32 s32, s32, 0x2000
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB3_2 ; GCN-NEXT: s_cbranch_execz BB3_2
; GCN-NEXT: ; %bb.1: ; %bb.0 ; GCN-NEXT: ; %bb.1: ; %bb.0
; GCN-NEXT: s_add_i32 s6, s32, 0x1000 ; GCN-NEXT: s_add_i32 s6, s32, 0x1000
; GCN-NEXT: s_andn2_b32 s6, s6, 63 ; GCN-NEXT: s_and_b32 s6, s6, 0xfffff000
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: v_mov_b32_e32 v5, s6 ; GCN-NEXT: v_mov_b32_e32 v5, s6
; GCN-NEXT: v_mov_b32_e32 v6, 1 ; GCN-NEXT: v_mov_b32_e32 v6, 1
; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen ; GCN-NEXT: buffer_store_dword v2, v5, s[0:3], 0 offen
; GCN-NEXT: buffer_store_dword v6, v5, s[0:3], 0 offen offset:4 ; GCN-NEXT: buffer_store_dword v6, v5, s[0:3], 0 offen offset:4
; GCN-NEXT: v_lshl_add_u32 v2, v3, 2, s6 ; GCN-NEXT: v_lshl_add_u32 v2, v3, 2, s6
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4 ; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4
Show All 37 Lines