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Differential D80287

[AMDGPU][MC][GFX8+] Enabled clamp for v_mul_i32_i24_e64 and v_mul_u32_u24_e64
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Authored by dp on May 20 2020, 3:52 AM.

Details

Reviewers
arsenm
rampitec
Commits
rG933ebc4078b7: [AMDGPU][MC][GFX8+] Enabled clamp for v_mul_i32_i24_e64 and v_mul_u32_u24_e64
Summary

See Bug 45925

Diff Detail

Event Timeline

dp created this revision.May 20 2020, 3:52 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 20 2020, 3:52 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
arsenm accepted this revision.May 20 2020, 5:47 AM
This revision is now accepted and ready to land.May 20 2020, 5:47 AM
Closed by commit rG933ebc4078b7: [AMDGPU][MC][GFX8+] Enabled clamp for v_mul_i32_i24_e64 and v_mul_u32_u24_e64 (authored by dp). · Explain WhyMay 22 2020, 4:45 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
6 lines
MC/
AMDGPU/
6 lines
12 lines
Disassembler/
AMDGPU/
6 lines
6 lines

Diff 265707

llvm/lib/Target/AMDGPU/VOP2Instructions.td

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def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>; def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, []>;
let isCommutable = 1 in { let isCommutable = 1 in {
defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>; defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>;
defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>; defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>;
defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">; defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>; defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>; defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>;
defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>; defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32_ARITH, AMDGPUmul_i24>;
defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>; defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_i24>;
defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>; defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32_ARITH, AMDGPUmul_u24>;
defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>; defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_PAT_GEN<VOP_I32_I32_I32, 2>, AMDGPUmulhi_u24>;
defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>; defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum_like>;
defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>; defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum_like>;
defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>; defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smin>;
defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>; defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_PAT_GEN<VOP_I32_I32_I32>, smax>;
defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>; defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>; defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">; defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
--- ---
name: mul_u24_vsv name: mul_u24_vsv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: mul_u24_vsv ; GCN-LABEL: name: mul_u24_vsv
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]] ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: mul_u24_vvs name: mul_u24_vvs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0 liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: mul_u24_vvs ; GCN-LABEL: name: mul_u24_vvs
; GCN: liveins: $sgpr0, $vgpr0 ; GCN: liveins: $sgpr0, $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]] ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0 %1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: mul_u24_vvv name: mul_u24_vvv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0, $vgpr1 liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: mul_u24_vvv ; GCN-LABEL: name: mul_u24_vvv
; GCN: liveins: $vgpr0, $vgpr1 ; GCN: liveins: $vgpr0, $vgpr1
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], implicit $exec ; GCN: [[V_MUL_U32_U24_e64_:%[0-9]+]]:vgpr_32 = V_MUL_U32_U24_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]] ; GCN: S_ENDPGM 0, implicit [[V_MUL_U32_U24_e64_]]
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1 %1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1 %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mul.u24), %0, %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/MC/AMDGPU/gfx10_asm_all.s

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// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x83,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x83,0x01,0x00]
v_mul_i32_i24_e64 v5, v1, 0.5 v_mul_i32_i24_e64 v5, v1, 0.5
// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xe1,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xe1,0x01,0x00]
v_mul_i32_i24_e64 v5, v1, -4.0 v_mul_i32_i24_e64 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xef,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xef,0x01,0x00]
v_mul_i32_i24_e64 v5, v1, -4.0 clamp
// GFX10: encoding: [0x05,0x80,0x09,0xd5,0x01,0xef,0x01,0x00]
v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06] // GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// GFX10: encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06] // GFX10: encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06] // GFX10: encoding: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
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// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x83,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x83,0x01,0x00]
v_mul_u32_u24_e64 v5, v1, 0.5 v_mul_u32_u24_e64 v5, v1, 0.5
// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xe1,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xe1,0x01,0x00]
v_mul_u32_u24_e64 v5, v1, -4.0 v_mul_u32_u24_e64 v5, v1, -4.0
// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xef,0x01,0x00] // GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xef,0x01,0x00]
v_mul_u32_u24_e64 v5, v1, -4.0 clamp
// GFX10: encoding: [0x05,0x80,0x0b,0xd5,0x01,0xef,0x01,0x00]
v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06] // GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// GFX10: encoding: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06] // GFX10: encoding: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06] // GFX10: encoding: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
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llvm/test/MC/AMDGPU/vop3.s

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v_mul_f32 v1, v3, s5 v_mul_f32 v1, v3, s5
// SICI: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x10,0xd2,0x03,0x0b,0x00,0x00] // SICI: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x10,0xd2,0x03,0x0b,0x00,0x00]
// VI: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x05,0xd1,0x03,0x0b,0x00,0x00] // VI: v_mul_f32_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x05,0xd1,0x03,0x0b,0x00,0x00]
v_mul_i32_i24 v1, v3, s5 v_mul_i32_i24 v1, v3, s5
// SICI: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x12,0xd2,0x03,0x0b,0x00,0x00] // SICI: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x12,0xd2,0x03,0x0b,0x00,0x00]
// VI: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x06,0xd1,0x03,0x0b,0x00,0x00] // VI: v_mul_i32_i24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x06,0xd1,0x03,0x0b,0x00,0x00]
v_mul_i32_i24 v1, v3, s5 clamp
// NOSICI: error: integer clamping is not supported on this GPU
// VI: v_mul_i32_i24_e64 v1, v3, s5 clamp ; encoding: [0x01,0x80,0x06,0xd1,0x03,0x0b,0x00,0x00]
v_mul_u32_u24 v1, v3, s5
// SICI: v_mul_u32_u24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x16,0xd2,0x03,0x0b,0x00,0x00]
// VI: v_mul_u32_u24_e64 v1, v3, s5 ; encoding: [0x01,0x00,0x08,0xd1,0x03,0x0b,0x00,0x00]
v_mul_u32_u24 v1, v3, s5 clamp
// NOSICI: error: integer clamping is not supported on this GPU
// VI: v_mul_u32_u24_e64 v1, v3, s5 clamp ; encoding: [0x01,0x80,0x08,0xd1,0x03,0x0b,0x00,0x00]
v_mac_f32_e64 v0, v1, v2 v_mac_f32_e64 v0, v1, v2
// SICI: v_mac_f32_e64 v0, v1, v2 ; encoding: [0x00,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00] // SICI: v_mac_f32_e64 v0, v1, v2 ; encoding: [0x00,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00]
// VI: v_mac_f32_e64 v0, v1, v2 ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x00] // VI: v_mac_f32_e64 v0, v1, v2 ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
v_mac_f32_e64 v0, v1, v2 clamp v_mac_f32_e64 v0, v1, v2 clamp
// SICI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x08,0x3e,0xd2,0x01,0x05,0x02,0x00] // SICI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x08,0x3e,0xd2,0x01,0x05,0x02,0x00]
// VI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x00] // VI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
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llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

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0x05,0x00,0x09,0xd5,0xff,0x05,0x02,0x00 0x05,0x00,0x09,0xd5,0xff,0x05,0x02,0x00
# GFX10: v_mul_i32_i24_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x09,0xd5,0x6b,0x04,0x02,0x00] # GFX10: v_mul_i32_i24_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x09,0xd5,0x6b,0x04,0x02,0x00]
0x05,0x00,0x09,0xd5,0x6b,0x04,0x02,0x00 0x05,0x00,0x09,0xd5,0x6b,0x04,0x02,0x00
# GFX10: v_mul_i32_i24_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x09,0xd5,0x6a,0x04,0x02,0x00] # GFX10: v_mul_i32_i24_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x09,0xd5,0x6a,0x04,0x02,0x00]
0x05,0x00,0x09,0xd5,0x6a,0x04,0x02,0x00 0x05,0x00,0x09,0xd5,0x6a,0x04,0x02,0x00
# GFX10: v_mul_i32_i24_e64 v5, vcc_lo, v2 clamp ; encoding: [0x05,0x80,0x09,0xd5,0x6a,0x04,0x02,0x00]
0x05,0x80,0x09,0xd5,0x6a,0x04,0x02,0x00
# GFX10: v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06] # GFX10: v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06 0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06
# GFX10: v_mul_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06] # GFX10: v_mul_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06]
0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06 0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06
# GFX10: v_mul_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06] # GFX10: v_mul_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06]
0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06 0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06
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0x05,0x00,0x0b,0xd5,0xff,0x05,0x02,0x00 0x05,0x00,0x0b,0xd5,0xff,0x05,0x02,0x00
# GFX10: v_mul_u32_u24_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x0b,0xd5,0x6b,0x04,0x02,0x00] # GFX10: v_mul_u32_u24_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x0b,0xd5,0x6b,0x04,0x02,0x00]
0x05,0x00,0x0b,0xd5,0x6b,0x04,0x02,0x00 0x05,0x00,0x0b,0xd5,0x6b,0x04,0x02,0x00
# GFX10: v_mul_u32_u24_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x0b,0xd5,0x6a,0x04,0x02,0x00] # GFX10: v_mul_u32_u24_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x0b,0xd5,0x6a,0x04,0x02,0x00]
0x05,0x00,0x0b,0xd5,0x6a,0x04,0x02,0x00 0x05,0x00,0x0b,0xd5,0x6a,0x04,0x02,0x00
# GFX10: v_mul_u32_u24_e64 v5, vcc_lo, v2 clamp ; encoding: [0x05,0x80,0x0b,0xd5,0x6a,0x04,0x02,0x00]
0x05,0x80,0x0b,0xd5,0x6a,0x04,0x02,0x00
# GFX10: v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06] # GFX10: v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06 0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06
# GFX10: v_mul_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06] # GFX10: v_mul_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06]
0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06 0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06
# GFX10: v_mul_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06] # GFX10: v_mul_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06]
0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06 0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06
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llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt

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0x02 0x07 0x02 0x08 0x02 0x07 0x02 0x08
# VI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a] # VI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
0x02 0x07 0x02 0x0a 0x02 0x07 0x02 0x0a
# VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c] # VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
0x02 0x07 0x02 0x0c 0x02 0x07 0x02 0x0c
# VI: v_mul_i32_i24_e64 v1, v2, v3 clamp ; encoding: [0x01,0x80,0x06,0xd1,0x02,0x07,0x02,0x00]
0x01 0x80 0x06 0xd1 0x02 0x07 0x02 0x00
# VI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e] # VI: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
0x02 0x07 0x02 0x0e 0x02 0x07 0x02 0x0e
# VI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10] # VI: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
0x02 0x07 0x02 0x10 0x02 0x07 0x02 0x10
# VI: v_mul_u32_u24_e64 v1, v3, s5 clamp ; encoding: [0x01,0x80,0x08,0xd1,0x03,0x0b,0x00,0x00]
0x01 0x80 0x08 0xd1 0x03 0x0b 0x00 0x00
# VI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12] # VI: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
0x02 0x07 0x02 0x12 0x02 0x07 0x02 0x12
# VI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14] # VI: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
0x02 0x07 0x02 0x14 0x02 0x07 0x02 0x14
# VI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16] # VI: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
0x02 0x07 0x02 0x16 0x02 0x07 0x02 0x16
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