[WebAssembly] Implement i64x2.mul and remove i8x16.mul

[tlively]

Summary

This reflects changes in the spec proposal made since basic arithmetic
was first implemented.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

690

Can we delete this now then?

llvm/test/CodeGen/WebAssembly/simd-unsupported.ll

312

What caused this change?

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

690

No, it is still used down in MIN_S and friends.

llvm/test/CodeGen/WebAssembly/simd-unsupported.ll

312

The default legalization uses a bunch of SIMD operations rather than scalarizing. One of the SIMD operations it uses is multiplication, so now that multiplication is legal, popcnt is no longer scalarized.

clang/lib/Headers/wasm_simd128.h

 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u8x16_sub_saturate(v128_t __a, v128_t __b) {
   return (v128_t)__builtin_wasm_sub_saturate_u_i8x16((__i8x16)__a,
                                                      (__i8x16)__b);
 }
 
-static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_mul(v128_t __a,
-                                                           v128_t __b) {
-  return (v128_t)((__u8x16)__a * (__u8x16)__b);
-}
-
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_min(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)__builtin_wasm_min_s_i8x16((__i8x16)__a, (__i8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_min(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)__builtin_wasm_min_u_i8x16((__i8x16)__a, (__i8x16)__b);

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
         setOperationAction(Op, T, Custom);
 
     // Custom lower lane accesses to expand out variable indices
     for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT})
       for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
                      MVT::v2f64})
         setOperationAction(Op, T, Custom);
 
-    // There is no i64x2.mul instruction
-    // TODO: Actually, there is now. Implement it.
-    setOperationAction(ISD::MUL, MVT::v2i64, Expand);
+    // There is no i8x16.mul instruction
+    setOperationAction(ISD::MUL, MVT::v16i8, Expand);
 
     // There are no vector select instructions
     for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT})
       for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
                      MVT::v2f64})
         setOperationAction(Op, T, Expand);
 
     // Expand integer operations supported for scalars but not SIMD

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

foreach shifts = [[wasm_shl, SHL_v2i64],
                   [wasm_shr_u, SHR_U_v2i64]] in
 def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)),
           (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>;
 
 //===----------------------------------------------------------------------===//
 // Integer binary arithmetic
 //===----------------------------------------------------------------------===//
 
+multiclass SIMDBinaryIntNoI8x16<SDNode node, string name, bits<32> baseInst> {
+  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
+  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
+  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
+}
+
 multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
   defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 32)>;
 }
 
 multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
   defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 64)>;
 }
 
 multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
   defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 96)>;
 }
 
 // Integer addition: add / add_saturate_s / add_saturate_u
 let isCommutable = 1 in {
 defm ADD : SIMDBinaryInt<add, "add", 110>;
 defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>;
 defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 112>;
 } // isCommutable = 1
 
 // Integer subtraction: sub / sub_saturate_s / sub_saturate_u
 defm SUB : SIMDBinaryInt<sub, "sub", 113>;
 defm SUB_SAT_S :
   SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 114>;
 defm SUB_SAT_U :
   SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 115>;
 
 // Integer multiplication: mul
 let isCommutable = 1 in
-defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 117>;
+defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>;
 
 // Integer min_s / min_u / max_s / max_u
 let isCommutable = 1 in {
 defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>;
 defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>;
 defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>;
 defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>;
 } // isCommutable = 1

llvm/test/CodeGen/WebAssembly/simd-arith.ll

 ; SIMD128-NEXT: .functype sub_v16i8 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i8x16.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = sub <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
+; i8x16.mul is not in spec
 ; CHECK-LABEL: mul_v16i8:
 ; NO-SIMD128-NOT: i8x16
-; SIMD128-NEXT: .functype mul_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: i8x16.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
-; SIMD128-NEXT: return $pop[[R]]{{$}}
+; SIMD128-NOT: i8x16.mul
+; SIMD128: i8x16.extract_lane_u
+; SIMD128: i32.mul
 define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = mul <16 x i8> %x, %y
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: min_s_v16i8:
 ; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype min_s_v16i8 (v128, v128) -> (v128){{$}}

 ; SIMD128-NEXT: .functype sub_v2i64 (v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: i64x2.sub $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = sub <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
-; v2i64.mul is not in spec
 ; CHECK-LABEL: mul_v2i64:
 ; NO-SIMD128-NOT: i64x2
-; SIMD128-NOT: i64x2.mul
-; SIMD128: i64x2.extract_lane
-; SIMD128: i64.mul
+; SIMD128-NEXT: .functype mul_v2i64 (v128, v128) -> (v128){{$}}
+; SIMD128: i64x2.mul $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = mul <2 x i64> %x, %y
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: neg_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-NEXT: .functype neg_v2i64 (v128) -> (v128){{$}}

llvm/test/CodeGen/WebAssembly/simd-unsupported.ll

 ; CHECK-LABEL: cttz_v2i64_undef:
 ; CHECK: i64.ctz
 define <2 x i64> @cttz_v2i64_undef(<2 x i64> %x) {
   %v = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %x, i1 true)
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: ctpop_v2i64:
-; CHECK: i64.popcnt
+; Note: expansion does not use i64.popcnt
+; CHECK: v128.and
 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
 define <2 x i64> @ctpop_v2i64(<2 x i64> %x) {
   %v = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x)
   ret <2 x i64> %v
 }
 
 ; CHECK-LABEL: sdiv_v2i64:
 ; CHECK: i64.div_s

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     i8x16.sub
 
     # CHECK: i8x16.sub_saturate_s # encoding: [0xfd,0x72]
     i8x16.sub_saturate_s
 
     # CHECK: i8x16.sub_saturate_u # encoding: [0xfd,0x73]
     i8x16.sub_saturate_u
 
-    # CHECK: i8x16.mul # encoding: [0xfd,0x75]
-    i8x16.mul
-
     # CHECK: i8x16.min_s # encoding: [0xfd,0x76]
     i8x16.min_s
 
     # CHECK: i8x16.min_u # encoding: [0xfd,0x77]
     i8x16.min_u
 
     # CHECK: i8x16.max_s # encoding: [0xfd,0x78]
     i8x16.max_s
main:
     i64x2.shr_u
 
     # CHECK: i64x2.add # encoding: [0xfd,0xce,0x01]
     i64x2.add
 
     # CHECK: i64x2.sub # encoding: [0xfd,0xd1,0x01]
     i64x2.sub
 
+    # CHECK: i64x2.mul # encoding: [0xfd,0xd5,0x01]
+    i64x2.mul
+
     # CHECK: f32x4.abs # encoding: [0xfd,0xe0,0x01]
     f32x4.abs
 
     # CHECK: f32x4.neg # encoding: [0xfd,0xe1,0x01]
     f32x4.neg
 
     # CHECK: f32x4.sqrt # encoding: [0xfd,0xe3,0x01]
     f32x4.sqrt