[PowerPC] add more high latency opcodes for machine combiner pass

[shchenz]

Summary

This pass adds more high latency associate and commutative opcodes for machine combiner pass on PowerPC.

For now, machine combiner pass on PowerPC only reassociates the operations which have latency no less than 5 based on Power9 UM.

[steven.zhang]

LGTM, thank you for adding this.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
   NewMI2.clearFlag(MachineInstr::MIFlag::NoSWrap);
   NewMI2.clearFlag(MachineInstr::MIFlag::NoUWrap);
   NewMI2.clearFlag(MachineInstr::MIFlag::IsExact);
 }
 
 // This function does not list all associative and commutative operations, but
 // only those worth feeding through the machine combiner in an attempt to
 // reduce the critical path. Mostly, this means floating-point operations,
-// because they have high latencies (compared to other operations, such and
+// because they have high latencies(>=5) (compared to other operations, such as
 // and/or, which are also associative and commutative, but have low latencies).
 bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   switch (Inst.getOpcode()) {
+  // Floating point:
   // FP Add:
   case PPC::FADD:
   case PPC::FADDS:
   // FP Multiply:
   case PPC::FMUL:
   case PPC::FMULS:
   // Altivec Add:
   case PPC::VADDFP:
bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   case PPC::QVFADDS:
   case PPC::QVFADDSs:
   // QPX Multiply:
   case PPC::QVFMUL:
   case PPC::QVFMULS:
   case PPC::QVFMULSs:
     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
+  // Fixed point:
+  // Multiply:
+  case PPC::MULHD:
+  case PPC::MULLD:
+  case PPC::MULHW:
+  case PPC::MULLW:
+    return true;
   default:
     return false;
   }
 }
 
 bool PPCInstrInfo::getMachineCombinerPatterns(
     MachineInstr &Root,
     SmallVectorImpl<MachineCombinerPattern> &Patterns) const {

llvm/test/CodeGen/PowerPC/machine-combiner.ll

define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
   %t1 = fmul double %x2, %t0
   %t2 = fmul double %x3, %t1
   ret double %t2
 }
 
 define i32 @reassociate_mullw(i32 %x0, i32 %x1, i32 %x2, i32 %x3) {
 ; FIXPOINT-LABEL: reassociate_mullw:
 ; FIXPOINT:       # %bb.0:
-; FIXPOINT:       mullw 3, 3, 4
-; FIXPOINT:       mullw 3, 3, 5
-; FIXPOINT:       mullw 3, 3, 6
+; FIXPOINT:       mullw [[REG0:[0-9]+]], 3, 4
+; FIXPOINT:       mullw [[REG1:[0-9]+]], 5, 6
+; FIXPOINT:       mullw 3, [[REG0]], [[REG1]]
 ; FIXPOINT-NEXT:  blr
 
   %t0 = mul i32 %x0, %x1
   %t1 = mul i32 %t0, %x2
   %t2 = mul i32 %t1, %x3
   ret i32 %t2
 }
 
 define i64 @reassociate_mulld(i64 %x0, i64 %x1, i64 %x2, i64 %x3) {
 ; FIXPOINT-LABEL: reassociate_mulld:
 ; FIXPOINT:       # %bb.0:
-; FIXPOINT:       mulld 3, 3, 4
-; FIXPOINT:       mulld 3, 3, 5
-; FIXPOINT:       mulld 3, 3, 6
+; FIXPOINT:       mulld [[REG0:[0-9]+]], 3, 4
+; FIXPOINT:       mulld [[REG1:[0-9]+]], 5, 6
+; FIXPOINT:       mulld 3, [[REG0]], [[REG1]]
 ; FIXPOINT-NEXT:  blr
 
   %t0 = mul i64 %x0, %x1
   %t1 = mul i64 %t0, %x2
   %t2 = mul i64 %t1, %x3
   ret i64 %t2
 }