[GlobalISel] Don't combine instructions which are fed by memory instructions.

[paquette]

Summary

If we have a memory instruction (e.g. a load), we shouldn't combine it away in some trivial combine.

It's possible that, say, a call lives between the instructions. This could modify the value loaded, making the load instructions not safe to fold.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1542

Could also consider if the load is invariant

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1542

Something like == G_LOAD && isDereferenceableInvariantLoad?

[paquette]

Add case for dereferenceable invariant loads

[aemerson]

LGTM.

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

if (!MOP1.isReg() || !MOP2.isReg())
     return false;
   MachineInstr *I1 = getDefIgnoringCopies(MOP1.getReg(), MRI);
   if (!I1)
     return false;
   MachineInstr *I2 = getDefIgnoringCopies(MOP2.getReg(), MRI);
   if (!I2)
     return false;
 
+  // If we have an instruction which loads or stores, we can't guarantee that
+  // it is identical.
+  //
+  // For example, we may have
+  //
+  // %x1 = G_LOAD %addr (load N from @somewhere)
+  // ...
+  // call @foo
+  // ...
+  // %x2 = G_LOAD %addr (load N from @somewhere)
+  // ...
+  // %or = G_OR %x1, %x2
+  //
+  // It's possible that @foo will modify whatever lives at the address we're
+  // loading from. To be safe, let's just assume that all loads and stores
+  // are different.
+  if (I1->mayLoadOrStore())
+    return false;
+
   // Check for physical registers on the instructions first to avoid cases like
   // this:
   //
   // %a = COPY $physreg
   // ...
   // SOMETHING implicit-def $physreg
   // ...
   // %b = COPY $physreg

llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-not-really-equiv-insts.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+  @g = external hidden unnamed_addr global i32, align 4
+  define void @not_necessarily_equiv_loads() local_unnamed_addr { ret void }
+...
+---
+name:            not_necessarily_equiv_loads
+tracksRegLiveness: true
+machineFunctionInfo: {}
+body:             |
+  bb.0:
+
+    ; %load1 || %load2 == %load1 is not necessarily true, even though they
+    ; both load from the same address. Whatever is in that address may be
+    ; changed by another instruction which appears between them.
+    ;
+    ; Check that we don't remove the G_OR.
+
+    ; CHECK-LABEL: name: not_necessarily_equiv_loads
+    ; CHECK: %ptr:_(p0) = G_GLOBAL_VALUE @g
+    ; CHECK: %load1:_(s32) = G_LOAD %ptr(p0) :: (load 4 from @g)
+    ; CHECK: %load2:_(s32) = G_LOAD %ptr(p0) :: (load 4 from @g)
+    ; CHECK: %or:_(s32) = G_OR %load2, %load1
+    ; CHECK: G_STORE %or(s32), %ptr(p0) :: (store 4 into @g)
+    ; CHECK: RET_ReallyLR
+    %ptr:_(p0) = G_GLOBAL_VALUE @g
+    %load1:_(s32) = G_LOAD %ptr(p0) :: (load 4 from @g)
+    %load2:_(s32) = G_LOAD %ptr(p0) :: (load 4 from @g)
+    %or:_(s32) = G_OR %load2, %load1
+    G_STORE %or(s32), %ptr(p0) :: (store 4 into @g)
+    RET_ReallyLR