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Differential D79006

[Hexagon] Handle cases for subregisters.
ClosedPublic

Authored by bcain on Apr 28 2020, 7:36 AM.

Details

Reviewers
ssarda
kparzysz
Summary

While restoring latency, check if any of the registers of source instruction is a subregister of the successor instructions apart from being same register.

Diff Detail

Event Timeline

bcain created this revision.Apr 28 2020, 7:36 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2020, 7:36 AM
Herald added a subscriber: hiraditya. · View Herald Transcript
bcain updated this revision to Diff 260637.Apr 28 2020, 7:57 AM

add -march=hexagon to test case

Harbormaster completed remote builds in B54970: Diff 260637.Apr 28 2020, 9:06 AM
Harbormaster completed remote builds in B54966: Diff 260632.Apr 28 2020, 10:11 AM
kparzysz accepted this revision.Apr 29 2020, 11:27 AM
This revision is now accepted and ready to land.Apr 29 2020, 11:27 AM
bcain updated this revision to Diff 261270.Apr 30 2020, 9:51 AM

simplified test case

Harbormaster failed remote builds in B55328: Diff 261270!Apr 30 2020, 11:15 AM
bcain closed this revision.Jun 3 2020, 7:56 AM

Revision Contents

PathSize
llvm/
lib/
Target/
Hexagon/
13 lines
test/
CodeGen/
Hexagon/
68 lines

Diff 260637

llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Linesvoid HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
MachineInstr *SrcI = Src->getInstr(); MachineInstr *SrcI = Src->getInstr();
for (auto &I : Src->Succs) { for (auto &I : Src->Succs) {
if (!I.isAssignedRegDep() || I.getSUnit() != Dst) if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
continue; continue;
unsigned DepR = I.getReg(); unsigned DepR = I.getReg();
int DefIdx = -1; int DefIdx = -1;
for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) { for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
const MachineOperand &MO = SrcI->getOperand(OpNum); const MachineOperand &MO = SrcI->getOperand(OpNum);
if (MO.isReg() && MO.isDef() && MO.getReg() == DepR) bool IsSameOrSubReg = false;
if (MO.isReg()) {
unsigned MOReg = MO.getReg();
if (Register::isVirtualRegister(DepR)) {
IsSameOrSubReg = (MOReg == DepR);
} else {
IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
}
if (MO.isDef() && IsSameOrSubReg)
DefIdx = OpNum; DefIdx = OpNum;
} }
}
assert(DefIdx >= 0 && "Def Reg not found in Src MI"); assert(DefIdx >= 0 && "Def Reg not found in Src MI");
MachineInstr *DstI = Dst->getInstr(); MachineInstr *DstI = Dst->getInstr();
SDep T = I; SDep T = I;
for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) { for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
const MachineOperand &MO = DstI->getOperand(OpNum); const MachineOperand &MO = DstI->getOperand(OpNum);
if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) { if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI, int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
DefIdx, *DstI, OpNum)); DefIdx, *DstI, OpNum));
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/test/CodeGen/Hexagon/check-subregister-for-latency.ll

  • This file was added.
; RUN: llc -march=hexagon -mcpu=hexagonv67t < %s
; REQUIRES: asserts
; ModuleID = 'bugpoint-reduced-simplified.bc'
source_filename = "ld-temp.o"
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
%struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564 = type { double, double, double, double, double, double, i32, double, double, double, double, i8*, i8, [9 x i8], double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, [200 x i8*], [32 x i8*], [32 x i8], i32 }
define hidden fastcc void @fv_update_nonbon() unnamed_addr #0 {
entry:
%qxx295 = getelementptr inbounds %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564, %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564* null, i32 0, i32 33
%qxy307 = getelementptr inbounds %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564, %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564* null, i32 0, i32 34
br label %for.body205
for.body205: ; preds = %for.body205, %entry
%arrayidx206.phi = phi i32* [ undef, %entry ], [ %arrayidx206.inc, %for.body205 ]
%0 = load i32, i32* %arrayidx206.phi, align 1, !tbaa !1
%arrayidx207 = getelementptr inbounds [0 x %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564*], [0 x %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564*]* null, i32 0, i32 %0
%1 = load %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564*, %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564** %arrayidx207, align 1, !tbaa !5
%2 = load double, double* undef, align 1, !tbaa !7
%div211 = fdiv double 1.000000e+00, %2
%mul236 = fmul double %div211, 0.000000e+00
%mul237 = fmul double %div211, 0.000000e+00
%mul240 = fmul double %mul236, -4.800000e+01
%mul241 = fmul double %mul237, 1.680000e+02
%mul244 = fmul double %div211, 0.000000e+00
%3 = load double, double* null, align 1, !tbaa !7
%mul250 = fmul double %div211, %3
%mul253 = fmul double %mul244, 0.000000e+00
%dpx254 = getelementptr inbounds %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564, %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564* %1, i32 0, i32 30
%sub255 = fsub double 0.000000e+00, %mul253
store double %sub255, double* %dpx254, align 8, !tbaa !9
%mul265 = fmul double %mul250, 0.000000e+00
%dpz266 = getelementptr inbounds %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564, %struct.ATOM.2.17.44.71.80.101.128.134.137.140.146.149.152.155.158.164.167.170.179.197.212.215.236.239.242.245.248.266.278.281.284.299.323.332.335.350.353.356.362.377.401.404.425.434.446.449.452.455.458.533.542.557.564* %1, i32 0, i32 32
%4 = load double, double* %dpz266, align 8, !tbaa !11
%sub267 = fsub double %4, %mul265
store double %sub267, double* %dpz266, align 8, !tbaa !11
%mul276 = fmul double %mul240, 0.000000e+00
%add277 = fadd double 0.000000e+00, %mul276
%mul280 = fmul double 0.000000e+00, %mul241
%add281 = fadd double %add277, %mul280
%sub296 = fsub double 0.000000e+00, %add281
store double %sub296, double* %qxx295, align 8, !tbaa !12
store double 0.000000e+00, double* %qxy307, align 8, !tbaa !13
%arrayidx206.inc = getelementptr i32, i32* %arrayidx206.phi, i32 1
br label %for.body205
}
attributes #0 = { "use-soft-float"="false" }
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"EnableSplitLTOUnit", i32 0}
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}
!5 = !{!6, !6, i64 0}
!6 = !{!"any pointer", !3, i64 0}
!7 = !{!8, !8, i64 0}
!8 = !{!"double", !3, i64 0}
!9 = !{!10, !8, i64 232}
!10 = !{!"", !8, i64 0, !8, i64 8, !8, i64 16, !8, i64 24, !8, i64 32, !8, i64 40, !2, i64 48, !8, i64 56, !8, i64 64, !8, i64 72, !8, i64 80, !6, i64 88, !3, i64 92, !3, i64 93, !8, i64 104, !8, i64 112, !8, i64 120, !8, i64 128, !8, i64 136, !8, i64 144, !8, i64 152, !8, i64 160, !8, i64 168, !8, i64 176, !8, i64 184, !8, i64 192, !8, i64 200, !8, i64 208, !8, i64 216, !8, i64 224, !8, i64 232, !8, i64 240, !8, i64 248, !8, i64 256, !8, i64 264, !8, i64 272, !8, i64 280, !8, i64 288, !8, i64 296, !3, i64 304, !3, i64 1104, !3, i64 1232, !2, i64 1264}
!11 = !{!10, !8, i64 248}
!12 = !{!10, !8, i64 256}
!13 = !{!10, !8, i64 264}