[VE] Update branch instructions

[kaz7]

Summary

Changing all mnemonic to match assembly instructions to simplify mnemonic
naming rules. This time update all branch instructions. This also change
to use %s10 register consitently.

Depends on D78887.

[simoll]

LGTM. Again, only some minor remarks.

llvm/lib/Target/VE/VEInstrInfo.cpp

28

unrelated change

207

Formatting. Please put the addMBB on the next line to follow the style of the code.

255

same

llvm/lib/Target/VE/VEInstrInfo.td

1129

In the tests below %lr has turned into %s10 . I suppose you could replace the asm string bsic %s10 here with bsic %lr to prevent this (at least for this pattern).

[kaz7]

Modify code to follow Simon-san's suggestions.

[kaz7]

llvm/lib/Target/VE/VEInstrInfo.cpp

28

Reverted it.

207

Clang format modified it as this. I reverted it. Thanks.

255

same

llvm/lib/Target/VE/VEInstrInfo.td

1129

I modified them to use %s10 register consistently. I'll write it in the summary later. Thank you for the suggestion.

[simoll]

Thanks for clarifying the %s10 change. LGTM :)

llvm/lib/Target/VE/VEAsmPrinter.cpp

static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD,
   SICInst.setOpcode(VE::SIC);
   SICInst.addOperand(RD);
   OutStreamer.emitInstruction(SICInst, STI);
 }
 
 static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2,
                      const MCSubtargetInfo &STI) {
   MCInst BSICInst;
-  BSICInst.setOpcode(VE::BSIC);
+  BSICInst.setOpcode(VE::BSICrii);
   BSICInst.addOperand(R1);
   BSICInst.addOperand(R2);
+  MCOperand czero = MCOperand::createImm(0);
+  BSICInst.addOperand(czero);
+  BSICInst.addOperand(czero);
   OutStreamer.emitInstruction(BSICInst, STI);
 }
 
 static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD,
                        const MCSubtargetInfo &STI) {
   MCInst LEAInst;
   LEAInst.setOpcode(VE::LEAzii);
   LEAInst.addOperand(RD);

llvm/lib/Target/VE/VEInstrInfo.cpp

 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #define DEBUG_TYPE "ve"
 
 using namespace llvm;
 
 #define GET_INSTRINFO_CTOR_DTOR
 #include "VEGenInstrInfo.inc"
 
 // Pin the vtable to this file.
 void VEInstrInfo::anchor() {}
static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) {
   case VECC::CC_EQNAN:  return VECC::CC_NE;
   case VECC::CC_GENAN:  return VECC::CC_L;
   case VECC::CC_LENAN:  return VECC::CC_G;
   case VECC::CC_AT:     return VECC::CC_AF;
   }
   llvm_unreachable("Invalid cond code");
 }
 
-// Treat br.l [BCR AT] as unconditional branch
+// Treat br.l [BRCF AT] as unconditional branch
 static bool isUncondBranchOpcode(int Opc) {
-  return Opc == VE::BCRLa || Opc == VE::BCRWa ||
-         Opc == VE::BCRDa || Opc == VE::BCRSa;
+  return Opc == VE::BRCFLa    || Opc == VE::BRCFWa    ||
+         Opc == VE::BRCFLa_nt || Opc == VE::BRCFWa_nt ||
+         Opc == VE::BRCFLa_t  || Opc == VE::BRCFWa_t  ||
+         Opc == VE::BRCFDa    || Opc == VE::BRCFSa    ||
+         Opc == VE::BRCFDa_nt || Opc == VE::BRCFSa_nt ||
+         Opc == VE::BRCFDa_t  || Opc == VE::BRCFSa_t;
 }
 
 static bool isCondBranchOpcode(int Opc) {
-  return Opc == VE::BCRLrr  || Opc == VE::BCRLir  ||
-         Opc == VE::BCRLrm0 || Opc == VE::BCRLrm1 ||
-         Opc == VE::BCRLim0 || Opc == VE::BCRLim1 ||
-         Opc == VE::BCRWrr  || Opc == VE::BCRWir  ||
-         Opc == VE::BCRWrm0 || Opc == VE::BCRWrm1 ||
-         Opc == VE::BCRWim0 || Opc == VE::BCRWim1 ||
-         Opc == VE::BCRDrr  || Opc == VE::BCRDir  ||
-         Opc == VE::BCRDrm0 || Opc == VE::BCRDrm1 ||
-         Opc == VE::BCRDim0 || Opc == VE::BCRDim1 ||
-         Opc == VE::BCRSrr  || Opc == VE::BCRSir  ||
-         Opc == VE::BCRSrm0 || Opc == VE::BCRSrm1 ||
-         Opc == VE::BCRSim0 || Opc == VE::BCRSim1;
+  return Opc == VE::BRCFLrr    || Opc == VE::BRCFLir    ||
+         Opc == VE::BRCFLrr_nt || Opc == VE::BRCFLir_nt ||
+         Opc == VE::BRCFLrr_t  || Opc == VE::BRCFLir_t  ||
+         Opc == VE::BRCFWrr    || Opc == VE::BRCFWir    ||
+         Opc == VE::BRCFWrr_nt || Opc == VE::BRCFWir_nt ||
+         Opc == VE::BRCFWrr_t  || Opc == VE::BRCFWir_t  ||
+         Opc == VE::BRCFDrr    || Opc == VE::BRCFDir    ||
+         Opc == VE::BRCFDrr_nt || Opc == VE::BRCFDir_nt ||
+         Opc == VE::BRCFDrr_t  || Opc == VE::BRCFDir_t  ||
+         Opc == VE::BRCFSrr    || Opc == VE::BRCFSir    ||
+         Opc == VE::BRCFSrr_nt || Opc == VE::BRCFSir_nt ||
+         Opc == VE::BRCFSrr_t  || Opc == VE::BRCFSir_t;
+}
+
+static bool isIndirectBranchOpcode(int Opc) {
+  return Opc == VE::BCFLari    || Opc == VE::BCFLari    ||
+         Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt ||
+         Opc == VE::BCFLari_t  || Opc == VE::BCFLari_t  ||
+         Opc == VE::BCFLari    || Opc == VE::BCFLari    ||
+         Opc == VE::BCFLari_nt || Opc == VE::BCFLari_nt ||
+         Opc == VE::BCFLari_t  || Opc == VE::BCFLari_t;
 }
 
 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
                             SmallVectorImpl<MachineOperand> &Cond) {
   Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm()));
   Cond.push_back(LastInst->getOperand(1));
   Cond.push_back(LastInst->getOperand(2));
   Target = LastInst->getOperand(3).getMBB();
bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
 
   // If the block ends with two unconditional branches, handle it.  The second
   // one is not executed.
   if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
     TBB = SecondLastInst->getOperand(0).getMBB();
     return false;
   }
 
-  // TODO ...likewise if it ends with an indirect branch followed by an unconditional
+  // ...likewise if it ends with an indirect branch followed by an unconditional
   // branch.
-  // if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
-  //   I = LastInst;
-  //   if (AllowModify)
-  //     I->eraseFromParent();
-  //   return true;
-  // }
+  if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
+    I = LastInst;
+    if (AllowModify)
+      I->eraseFromParent();
+    return true;
+  }
 
   // Otherwise, can't handle this.
   return true;
 }
 
 unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
                                    MachineBasicBlock *TBB,
                                    MachineBasicBlock *FBB,
                                    ArrayRef<MachineOperand> Cond,
                                    const DebugLoc &DL, int *BytesAdded) const {
   assert(TBB && "insertBranch must not be told to insert a fallthrough");
   assert((Cond.size() == 3 || Cond.size() == 0) &&
          "VE branch conditions should have three component!");
   assert(!BytesAdded && "code size not handled");
   if (Cond.empty()) {
     // Uncondition branch
     assert(!FBB && "Unconditional branch with multiple successors!");
-    BuildMI(&MBB, DL, get(VE::BCRLa))
+    BuildMI(&MBB, DL, get(VE::BRCFLa_t))
         .addMBB(TBB);
     return 1;
   }
 
   // Conditional branch
-  //   (BCRir CC sy sz addr)
+  //   (BRCFir CC sy sz addr)
   assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented");
 
   unsigned opc[2];
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   MachineFunction *MF = MBB.getParent();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   unsigned Reg = Cond[2].getReg();
   if (IsIntegerCC(Cond[0].getImm())) {
     if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
-      opc[0] = VE::BCRWir;
-      opc[1] = VE::BCRWrr;
+      opc[0] = VE::BRCFWir;
+      opc[1] = VE::BRCFWrr;
     } else {
-      opc[0] = VE::BCRLir;
-      opc[1] = VE::BCRLrr;
+      opc[0] = VE::BRCFLir;
+      opc[1] = VE::BRCFLrr;
     }
   } else {
     if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
-      opc[0] = VE::BCRSir;
-      opc[1] = VE::BCRSrr;
+      opc[0] = VE::BRCFSir;
+      opc[1] = VE::BRCFSrr;
     } else {
-      opc[0] = VE::BCRDir;
-      opc[1] = VE::BCRDrr;
+      opc[0] = VE::BRCFDir;
+      opc[1] = VE::BRCFDrr;
     }
   }
   if (Cond[1].isImm()) {
       BuildMI(&MBB, DL, get(opc[0]))
           .add(Cond[0]) // condition code
           .add(Cond[1]) // lhs
           .add(Cond[2]) // rhs
           .addMBB(TBB);
   } else {
       BuildMI(&MBB, DL, get(opc[1]))
           .add(Cond[0])
           .add(Cond[1])
           .add(Cond[2])
           .addMBB(TBB);
   }
 
   if (!FBB)
     return 1;
 
-  BuildMI(&MBB, DL, get(VE::BCRLa))
+  BuildMI(&MBB, DL, get(VE::BRCFLa_t))
       .addMBB(FBB);
   return 2;
 }
 
 unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB,
                                    int *BytesRemoved) const {
   assert(!BytesRemoved && "code size not handled");
 
   MachineBasicBlock::iterator I = MBB.end();
bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const {
   sinkMBB->splice(sinkMBB->begin(), BB,
                   std::next(std::next(MachineBasicBlock::iterator(MI))),
                   BB->end());
   sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
 
   // Next, add the true and fallthrough blocks as its successors.
   BB->addSuccessor(syscallMBB);
   BB->addSuccessor(sinkMBB);
-  BuildMI(BB, dl, TII.get(VE::BCRLrr))
+  BuildMI(BB, dl, TII.get(VE::BRCFLrr_t))
       .addImm(VECC::CC_IGE)
       .addReg(VE::SX11) // %sp
       .addReg(VE::SX8)  // %sl
       .addMBB(sinkMBB);
 
   BB = syscallMBB;
 
   // Update machine-CFG edges

llvm/lib/Target/VE/VEInstrInfo.td

def icond2cc : SDNodeXForm<cond, [{
   case ISD::SETULT: cc = VECC::CC_IL;  break;
   case ISD::SETULE: cc = VECC::CC_ILE; break;
   case ISD::SETUGT: cc = VECC::CC_IG;  break;
   case ISD::SETUGE: cc = VECC::CC_IGE; break;
   }
   return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
 }]>;
 
+def icond2ccSwap : SDNodeXForm<cond, [{
+  VECC::CondCode cc;
+  switch (N->get()) {
+  default:          llvm_unreachable("Unknown integer condition code!");
+  case ISD::SETEQ:  cc = VECC::CC_IEQ; break;
+  case ISD::SETNE:  cc = VECC::CC_INE; break;
+  case ISD::SETLT:  cc = VECC::CC_IG;  break;
+  case ISD::SETGT:  cc = VECC::CC_IL;  break;
+  case ISD::SETLE:  cc = VECC::CC_IGE; break;
+  case ISD::SETGE:  cc = VECC::CC_ILE; break;
+  case ISD::SETULT: cc = VECC::CC_IG;  break;
+  case ISD::SETULE: cc = VECC::CC_IGE; break;
+  case ISD::SETUGT: cc = VECC::CC_IL;  break;
+  case ISD::SETUGE: cc = VECC::CC_ILE; break;
+  }
+  return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
+}]>;
+
 def fcond2cc : SDNodeXForm<cond, [{
   VECC::CondCode cc;
   switch (N->get()) {
   default:          llvm_unreachable("Unknown float condition code!");
   case ISD::SETFALSE: cc = VECC::CC_AF;    break;
   case ISD::SETEQ:
   case ISD::SETOEQ:   cc = VECC::CC_EQ;    break;
   case ISD::SETNE:
def fcond2cc : SDNodeXForm<cond, [{
   case ISD::SETUGT:   cc = VECC::CC_GNAN;  break;
   case ISD::SETULE:   cc = VECC::CC_LENAN; break;
   case ISD::SETUGE:   cc = VECC::CC_GENAN; break;
   case ISD::SETTRUE:  cc = VECC::CC_AT;    break;
   }
   return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
 }]>;
 
+def fcond2ccSwap : SDNodeXForm<cond, [{
+  VECC::CondCode cc;
+  switch (N->get()) {
+  default:          llvm_unreachable("Unknown float condition code!");
+  case ISD::SETFALSE: cc = VECC::CC_AF;    break;
+  case ISD::SETEQ:
+  case ISD::SETOEQ:   cc = VECC::CC_EQ;    break;
+  case ISD::SETNE:
+  case ISD::SETONE:   cc = VECC::CC_NE;    break;
+  case ISD::SETLT:
+  case ISD::SETOLT:   cc = VECC::CC_G;     break;
+  case ISD::SETGT:
+  case ISD::SETOGT:   cc = VECC::CC_L;     break;
+  case ISD::SETLE:
+  case ISD::SETOLE:   cc = VECC::CC_GE;    break;
+  case ISD::SETGE:
+  case ISD::SETOGE:   cc = VECC::CC_LE;    break;
+  case ISD::SETO:     cc = VECC::CC_NUM;   break;
+  case ISD::SETUO:    cc = VECC::CC_NAN;   break;
+  case ISD::SETUEQ:   cc = VECC::CC_EQNAN; break;
+  case ISD::SETUNE:   cc = VECC::CC_NENAN; break;
+  case ISD::SETULT:   cc = VECC::CC_GNAN;  break;
+  case ISD::SETUGT:   cc = VECC::CC_LNAN;  break;
+  case ISD::SETULE:   cc = VECC::CC_GENAN; break;
+  case ISD::SETUGE:   cc = VECC::CC_LENAN; break;
+  case ISD::SETTRUE:  cc = VECC::CC_AT;    break;
+  }
+  return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32);
+}]>;
+
 // Addressing modes.
 def ADDRri : ComplexPattern<iPTR, 2, "selectADDRri", [frameindex], []>;
 
 def MEMri : Operand<iPTR> {
   let PrintMethod = "printMemASOperandASX";
   let MIOperandInfo = (ops ptr_rc, i64imm);
 }
 

 //    AS format in RRM format for host memory access uses "sz", "(sz)",
 //    or "disp(sz)".
 //
 // We defined them below.
 //
 // ASX format:
 //    MEMrri, MEMrii, MEMzri, MEMzii
 // AS format:
+//    MEMriASX, MEMziASX    : simple AS format
 //    well be added later.
 
 def ADDRrri : ComplexPattern<iPTR, 3, "selectADDRrri", [frameindex], []>;
 def ADDRrii : ComplexPattern<iPTR, 3, "selectADDRrii", [frameindex], []>;
 def ADDRzri : ComplexPattern<iPTR, 3, "selectADDRzri", [], []>;
 def ADDRzii : ComplexPattern<iPTR, 3, "selectADDRzii", [], []>;
 //
 // ASX assembly instrcution format:
def MEMzri : Operand<iPTR> {
   let MIOperandInfo = (ops i32imm /* = 0 */, ptr_rc, i32imm);
   let ParserMatchClass = VEMEMzriAsmOperand;
 }
 def MEMzii : Operand<iPTR> {
   let PrintMethod = "printMemASXOperand";
   let MIOperandInfo = (ops i32imm /* = 0 */, i32imm, i32imm);
   let ParserMatchClass = VEMEMziiAsmOperand;
 }
+// AS assembly instrcution format:
+def VEMEMriAsmOperand : AsmOperandClass {
+  let Name = "MEMri";
+  let ParserMethod = "parseMEMAsOperand";
+}
+def VEMEMziAsmOperand : AsmOperandClass {
+  let Name = "MEMzi";
+  let ParserMethod = "parseMEMAsOperand";
+}
+// AS generic assembly instruction format:
+def MEMriASX : Operand<iPTR> {
+  let PrintMethod = "printMemASOperandASX";
+  let MIOperandInfo = (ops ptr_rc, i32imm);
+  let ParserMatchClass = VEMEMriAsmOperand;
+}
+def MEMziASX : Operand<iPTR> {
+  let PrintMethod = "printMemASOperandASX";
+  let MIOperandInfo = (ops i32imm /* = 0 */, i32imm);
+  let ParserMatchClass = VEMEMziAsmOperand;
+}
 
 // Branch targets have OtherVT type.
 def brtarget32 : Operand<OtherVT> {
   let EncoderMethod = "getBranchTarget32OpValue";
 }
 
 def calltarget : Operand<i64> {
   let EncoderMethod = "getCallTargetOpValue";
multiclass CVTm<string opcStr, bits<8> opc, RegisterClass RCo, ValueType Tyo,
   def r : RR<opc, (outs RCo:$sx), (ins RCi:$sy),
              !strconcat(opcStr, " $sx, $sy"),
              [(set Tyo:$sx, (OpNode Tyi:$sy))]>;
   let cy = 0 in
   def i : RR<opc, (outs RCo:$sx), (ins simm7:$sy),
              !strconcat(opcStr, " $sx, $sy")>;
 }
 
-// Branch multiclass
-let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
-multiclass BCRm<string opcStr, string opcStrAt, bits<8> opc,
-                RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> {
-  def rr : CF<
-    opc, (outs),
-    (ins CCOp:$cf, RC:$sy, RC:$sz, brtarget32:$imm32),
-    !strconcat(opcStr, " $sy, $sz, $imm32")> {
-    let cy = 1;
-    let cz = 1;
-    let hasSideEffects = 0;
-  }
-  def ir : CF<
-    opc, (outs),
-    (ins CCOp:$cf, immOp:$sy, RC:$sz, brtarget32:$imm32),
-    !strconcat(opcStr, " $sy, $sz, $imm32")> {
-    let cy = 0;
-    let cz = 1;
-    let hasSideEffects = 0;
-  }
-  def rm0 : CF<
-    opc, (outs), (ins CCOp:$cf, RC:$sy, immOp2:$sz, brtarget32:$imm32),
-    !strconcat(opcStr, " $sy, (${sz})0, $imm32"), []> {
-    let cy = 1;
-    let cz = 0;
-    let sz{6} = 1;
-    let hasSideEffects = 0;
-  }
-  def rm1 : CF<
-    opc, (outs), (ins CCOp:$cf, RC:$sy, immOp2:$sz, brtarget32:$imm32),
-    !strconcat(opcStr, " $sy, (${sz})1, $imm32"), []> {
-    let cy = 1;
-    let cz = 0;
-    let hasSideEffects = 0;
-  }
-  def im0 : CF<
-    opc, (outs), (ins CCOp:$cf, immOp:$sy, immOp2:$sz, brtarget32:$imm32),
-    !strconcat(opcStr, " $sy, (${sz})0, $imm32"), []> {
-    let cy = 0;
-    let cz = 0;
-    let sz{6} = 1;
-    let hasSideEffects = 0;
-  }
-  def im1 : CF<
-    opc, (outs), (ins CCOp:$cf, immOp:$sy, immOp2:$sz, brtarget32:$imm32),
-    !strconcat(opcStr, " $sy, (${sz})1, $imm32"), []> {
-    let cy = 0;
-    let cz = 0;
-    let hasSideEffects = 0;
-  }
-  def a : CF<
-    opc, (outs), (ins brtarget32:$imm32),
-    !strconcat(opcStrAt, " $imm32"), []> {
-    let cy = 0;
-    let sy = 0;
-    let cz = 0;
-    let sz = 0;
-    let cf = 15;  /* AT */
-    let isBarrier = 1;
-    let hasSideEffects = 0;
-  }
+// Multiclass for branch instructions
+//   e.g. BCFL, BCFW, BCFD, and etc.
+let isBranch = 1, isTerminator = 1, isIndirectBranch = 1, hasSideEffects = 0 in
+multiclass BCbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond,
+                  Operand ADDR> {
+  let bpf = 0 /* NONE */ in
+  def "" : CF<opc, (outs), !con(cond, (ins ADDR:$addr)),
+              !strconcat(opcStr, " ", cmpStr, "$addr")>;
+  let bpf = 2 /* NOT TaKEN */ in
+  def _nt : CF<opc, (outs), !con(cond, (ins ADDR:$addr)),
+               !strconcat(opcStr, ".nt ", cmpStr, "$addr")>;
+  let bpf = 3 /* TaKEN */ in
+  def _t : CF<opc, (outs), !con(cond, (ins ADDR:$addr)),
+              !strconcat(opcStr, ".t ", cmpStr, "$addr")>;
+}
+multiclass BCtgm<string opcStr, string cmpStr, bits<8> opc, dag cond> {
+  defm ri : BCbpfm<opcStr, cmpStr, opc, cond, MEMriASX>;
+  let cz = 0 in defm zi : BCbpfm<opcStr, cmpStr, opc, cond, MEMziASX>;
+}
+multiclass BCm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,
+               RegisterClass RC, Operand immOp> {
+  let DecoderMethod = "DecodeBranchCondition" in
+  defm r : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, RC:$comp)>;
+  let DecoderMethod = "DecodeBranchCondition", cy = 0 in
+  defm i : BCtgm<opcStr, "$comp, ", opc, (ins CCOp:$cond, immOp:$comp)>;
+  let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0,
+      cf = 15 /* AT */, isBarrier = 1 in
+  defm a : BCtgm<opcStrAt, "", opc, (ins)>;
+  let DecoderMethod = "DecodeBranchConditionAlways", cy = 0, sy = 0,
+      cf = 0 /* AF */ in
+  defm na : BCtgm<opcStrAf, "", opc, (ins)>;
+}
+
+// Multiclass for relative branch instructions
+//   e.g. BRCFL, BRCFW, BRCFD, and etc.
+let isBranch = 1, isTerminator = 1, hasSideEffects = 0 in
+multiclass BCRbpfm<string opcStr, string cmpStr, bits<8> opc, dag cond> {
+  let bpf = 0 /* NONE */ in
+  def "" : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)),
+              !strconcat(opcStr, " ", cmpStr, "$imm32")>;
+  let bpf = 2 /* NOT TaKEN */ in
+  def _nt : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)),
+               !strconcat(opcStr, ".nt ", cmpStr, "$imm32")>;
+  let bpf = 3 /* TaKEN */ in
+  def _t : CF<opc, (outs), !con(cond, (ins brtarget32:$imm32)),
+              !strconcat(opcStr, ".t ", cmpStr, "$imm32")>;
+}
+multiclass BCRm<string opcStr, string opcStrAt, string opcStrAf, bits<8> opc,
+               RegisterClass RC, Operand immOp> {
+  defm rr : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, RC:$sy, RC:$sz)>;
+  let cy = 0 in
+  defm ir : BCRbpfm<opcStr, "$sy, $sz, ", opc, (ins CCOp:$cf, immOp:$sy, RC:$sz)>;
+  let cy = 0, sy = 0, cz = 0, sz = 0, cf = 15 /* AT */, isBarrier = 1 in
+  defm a : BCRbpfm<opcStrAt, "", opc, (ins)>;
+  let cy = 0, sy = 0, cz = 0, sz = 0, cf = 0 /* AF */ in
+  defm na : BCRbpfm<opcStrAf, "", opc, (ins)>;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //
 // Define all scalar instructions defined in SX-Aurora TSUBASA Architecture
 // Guide here.  As those mnemonics, we use mnemonics defined in Vector Engine
 // Assembly Language Reference Manual.

 // Section 8.7.15 - CVS (Convert to Single-format)
 defm CVTSD : CVTm<"cvt.s.d", 0x1F, F32, f32, I64, f64, fpround>;
 
 // Section 8.7.16 - CVD (Convert to Double-format)
 defm CVTDS : CVTm<"cvt.d.s", 0x0F, I64, f64, F32, f32, fpextend>;
 
 // Section 8.7.17 - CVQ (Convert to Single-format)
 
-// Control-flow
+//-----------------------------------------------------------------------------
+// Section 8.8 - Branch instructions
+//-----------------------------------------------------------------------------
 
-// Jump instruction
-let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cy = 1, cz = 1,
-    isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasSideEffects = 0 in
-def BC : CF<
-    0x19, (outs), (ins CCOp:$cf, I64:$sy, brtarget32:$imm32),
-    "b.${cf}.l $sy, $imm32">;
-
-// Jump always instruction is treated as a special case of jump in order
-// to make finding unconditional jump easy.
-let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 15 /* AT */, cy = 0, sy = 0,
-    cz = 1,
-    isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1,
-    hasDelaySlot = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
-def BAri : CF<
-    0x19, (outs), (ins MEMri:$addr),
-    "b.l $addr",
-    [(brind ADDRri:$addr)]>;
-}
-
-// Jump never instruction is also a special case of jump.
-let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 0 /* AF */, cy = 1, sy = 0,
-    cz = 1,
-    isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasSideEffects = 0 in
-def BN : CF<
-    0x19, (outs), (ins brtarget32:$imm32),
-    "b.af.l $imm32">;
-
-// Return instruction is also a special case of jump.
-let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 15 /* AT */, cy = 0, sy = 0,
-    cz = 1, sz = 0x10 /* SX10 */, imm32 = 0, Uses = [SX10],
-    isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
-    isCodeGenOnly = 1, hasSideEffects = 0 in
-def RET : CF<
-    0x19, (outs), (ins),
-    "b.l (,%lr)",
-    [(retflag)]>;
-
-// Branch and Save IC
-
-let cx = 0, cy = 0, cy = 0, cz = 1, hasSideEffects = 0 /* , Uses = [IC] */ in
-def BSIC : RM<0x08, (outs), (ins I64:$sx, I64:$sz), "bsic $sx, (, ${sz})">;
-
-// Branch instruction
-let cx = 0, cx2 = 0, bpf = 0 /* NONE */ in
-defm BCRL : BCRm<"br${cf}.l", "br.l", 0x18, I64, i64, simm7, uimm6>;
-let cx = 1, cx2 = 0, bpf = 0 /* NONE */ in
-defm BCRW : BCRm<"br${cf}.w", "br.w", 0x18, I32, i32, simm7, uimm6>;
-let cx = 0, cx2 = 1, bpf = 0 /* NONE */ in
-defm BCRD : BCRm<"br${cf}.d", "br.d", 0x18, I64, f64, simm7, uimm6>;
-let cx = 1, cx2 = 1, bpf = 0 /* NONE */ in
-defm BCRS : BCRm<"br${cf}.s", "br.s", 0x18, F32, f32, simm7, uimm6>;
+// Section 8.8.1 - BC (Branch on Codition)
+defm BCFL : BCm<"b${cond}.l", "b.l", "baf.l", 0x19, I64, simm7>;
+
+// Indirect branch aliases
+def : Pat<(brind I64:$reg), (BCFLari_t $reg, 0)>;
+def : Pat<(brind tblockaddress:$imm), (BCFLazi_t 0, $imm)>;
+
+// Return instruction is a special case of jump.
+let Uses = [SX10], bpf = 3 /* TAKEN */, cf = 15 /* AT */, cy = 0, sy = 0,
+    sz = 10 /* SX10 */, imm32 = 0, isReturn = 1, isTerminator = 1,
+    isBarrier = 1, isCodeGenOnly = 1, hasSideEffects = 0 in
+def RET : CF<0x19, (outs), (ins), "b.l.t (, %s10)", [(retflag)]>;
+
+// Section 8.8.2 - BCS (Branch on Condition Single)
+defm BCFW : BCm<"b${cond}.w", "b.w", "baf.w", 0x1B, I32, simm7>;
+
+// Section 8.8.3 - BCF (Branch on Condition Floating Point)
+defm BCFD : BCm<"b${cond}.d", "b.d", "baf.d", 0x1C, I64, simm7fp>;
+let cx = 1 in
+defm BCFS : BCm<"b${cond}.s", "b.s", "baf.s", 0x1C, F32, simm7fp>;
+
+// Section 8.8.4 - BCR (Branch on Condition Relative)
+let cx = 0, cx2 = 0 in
+defm BRCFL : BCRm<"br${cf}.l", "br.l", "braf.l", 0x18, I64, simm7>;
+let cx = 1, cx2 = 0 in
+defm BRCFW : BCRm<"br${cf}.w", "br.w", "braf.w", 0x18, I32, simm7>;
+let cx = 0, cx2 = 1 in
+defm BRCFD : BCRm<"br${cf}.d", "br.d", "braf.d", 0x18, I64, simm7fp>;
+let cx = 1, cx2 = 1 in
+defm BRCFS : BCRm<"br${cf}.s", "br.s", "braf.s", 0x18, F32, simm7fp>;
+
+// Section 8.8.5 - BSIC (Branch and Save IC)
+let isCall = 1, hasSideEffects = 0, DecoderMethod = "DecodeCall" in
+defm BSIC : RMm<"bsic", 0x08, I64>;
+
+// Call instruction is a special case of BSIC.
+let Defs = [SX10], sx = 10 /* SX10 */, cy = 0, sy = 0, imm32 = 0,
+    isCall = 1, isCodeGenOnly = 1, hasSideEffects = 0 in
+def CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops),
+               "bsic %s10, (, $sz)", [(call i64:$sz)]>;
 
 let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in {
 let sy = 3 in
 def SHMri : RM<
     0x31, (outs), (ins MEMASri:$addr, I64:$sx),
     "shm.l $sx, $addr">;
 }
 
 let cx = 0, sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in
 def MONC : RR<
     0x3F, (outs), (ins),
     "monc">;
 
 // Save Instruction Counter
 
 let cx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 /* , Uses = [IC] */ in
 def SIC : RR<0x28, (outs I32:$sx), (ins), "sic $sx">;
 
 //===----------------------------------------------------------------------===//
 // Instructions for CodeGenOnly
 //===----------------------------------------------------------------------===//
 
-let isCodeGenOnly = 1 in {
-
-// Call instruction
-let Defs = [SX10], Uses = [SX11], hasDelaySlot = 1, isCall = 1, hasSideEffects = 0 in {
-let cx = 0, sx = 10, cy = 0, sy = 0, cz = 0, sz = 0 in
-def CALL : RM<
-    0x08, (outs), (ins calltarget:$imm32, variable_ops),
-    "bsic %lr, $imm32">;
-// use sz to represent a register
-let cx = 0, sx = 10, cy = 0, sy = 0, cz = 1, imm32 = 0 in
-def CALLr : RM<
-    0x08, (outs), (ins I64:$sz, variable_ops),
-    "bsic %lr, (,$sz)">;
-}
-
-}
-
 //===----------------------------------------------------------------------===//
 // Pattern Matchings
 //===----------------------------------------------------------------------===//
 
 // Small immediates.
 def : Pat<(i32 simm7:$val), (OR32im (LO7 $val), 0)>;
 def : Pat<(i64 simm7:$val), (ORim (LO7 $val), 0)>;
 // Medium immediates.

 // Address calculation and its optimization
 def : Pat<(VEhi texternalsym:$in), (LEASLzii 0, 0, texternalsym:$in)>;
 def : Pat<(VElo texternalsym:$in),
           (ANDrm (LEAzii 0, 0, texternalsym:$in), !add(32, 64))>;
 def : Pat<(add (VEhi texternalsym:$in1), (VElo texternalsym:$in2)),
           (LEASLrii (ANDrm (LEAzii 0, 0, texternalsym:$in2), !add(32, 64)), 0,
                     (texternalsym:$in1))>;
 
-// Calls
-def : Pat<(call tglobaladdr:$dst),
-          (CALL tglobaladdr:$dst)>;
-def : Pat<(call i64:$dst),
-          (CALLr i64:$dst)>;
-
 // Branches
-def : Pat<(br bb:$addr), (BCRLa bb:$addr)>;
+def : Pat<(br bb:$addr), (BRCFLa bb:$addr)>;
 
 // brcc
-def : Pat<(brcc CCSIOp:$cond, i32:$l, i32:$r, bb:$addr),
-          (BCRWrr (icond2cc $cond), $l, $r, bb:$addr)>;
-def : Pat<(brcc CCUIOp:$cond, i32:$l, i32:$r, bb:$addr),
-          (BCRWir (icond2cc $cond), 0, (CMPUWrr $r, $l), bb:$addr)>;
-def : Pat<(brcc CCSIOp:$cond, i64:$l, i64:$r, bb:$addr),
-          (BCRLrr (icond2cc $cond), $l, $r, bb:$addr)>;
-def : Pat<(brcc CCUIOp:$cond, i64:$l, i64:$r, bb:$addr),
-          (BCRLir (icond2cc $cond), 0, (CMPULrr $r, $l), bb:$addr)>;
-def : Pat<(brcc cond:$cond, f32:$l, f32:$r, bb:$addr),
-          (BCRSrr (fcond2cc $cond), $l, $r, bb:$addr)>;
-def : Pat<(brcc cond:$cond, f64:$l, f64:$r, bb:$addr),
-          (BCRDrr (fcond2cc $cond), $l, $r, bb:$addr)>;
+// integer brcc
+multiclass BRCCIm<ValueType ty, SDPatternOperator BrOpNode1,
+                 SDPatternOperator BrOpNode2,
+                 SDPatternOperator CmpOpNode1,
+                 SDPatternOperator CmpOpNode2> {
+  def : Pat<(brcc CCSIOp:$cond, ty:$l, simm7:$r, bb:$addr),
+            (BrOpNode2 (icond2ccSwap $cond), (LO7 $r), $l, bb:$addr)>;
+  def : Pat<(brcc CCSIOp:$cond, ty:$l, ty:$r, bb:$addr),
+            (BrOpNode1 (icond2cc $cond), $l, $r, bb:$addr)>;
+  def : Pat<(brcc CCUIOp:$cond, ty:$l, simm7:$r, bb:$addr),
+            (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode2 (LO7 $r), $l),
+                       bb:$addr)>;
+  def : Pat<(brcc CCUIOp:$cond, ty:$l, ty:$r, bb:$addr),
+            (BrOpNode2 (icond2cc $cond), 0, (CmpOpNode1 $r, $l), bb:$addr)>;
+}
+defm : BRCCIm<i32, BRCFWrr, BRCFWir, CMPUWrr, CMPUWir>;
+defm : BRCCIm<i64, BRCFLrr, BRCFLir, CMPULrr, CMPULir>;
+
+// floating point brcc
+multiclass BRCCFm<ValueType ty, SDPatternOperator BrOpNode1,
+                 SDPatternOperator BrOpNode2> {
+  def : Pat<(brcc cond:$cond, ty:$l, simm7fp:$r, bb:$addr),
+            (BrOpNode2 (fcond2ccSwap $cond), (LO7FP $r), $l, bb:$addr)>;
+  def : Pat<(brcc cond:$cond, ty:$l, ty:$r, bb:$addr),
+            (BrOpNode1 (fcond2cc $cond), $l, $r, bb:$addr)>;
+}
+defm : BRCCFm<f32, BRCFSrr, BRCFSir>;
+defm : BRCCFm<f64, BRCFDrr, BRCFDir>;
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 // GETGOT for PIC
 let Defs = [SX15 /* %got */, SX16 /* %plt */], hasSideEffects = 0 in {
   def GETGOT : Pseudo<(outs getGOT:$getpcseq), (ins), "$getpcseq">;

llvm/test/CodeGen/VE/branch1.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define signext i8 @func1(i8 signext %a, i8 signext %b) {
 ; CHECK-LABEL: func1:
 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    brle.w %s0, %s1, .LBB0_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB0_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB0_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    sla.w.sx %s0, %s0, 24
 ; CHECK-NEXT:    sra.w.sx %s0, %s0, 24
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp sgt i8 %a, %b

 ; CHECK-LABEL: func2:
 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    brle.w %s0, %s1, .LBB1_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB1_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB1_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp sgt i16 %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK-LABEL: func3:
 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    brle.w %s0, %s1, .LBB2_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB2_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB2_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp sgt i32 %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK-LABEL: func4:
 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    brle.l %s0, %s1, .LBB3_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB3_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB3_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp sgt i64 %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
 ; CHECK-NEXT:    brle.w 0, %s0, .LBB4_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB4_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB4_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp ugt i8 %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
 ; CHECK-NEXT:    brle.w 0, %s0, .LBB5_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB5_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB5_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp ugt i16 %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    cmpu.w %s0, %s1, %s0
 ; CHECK-NEXT:    brle.w 0, %s0, .LBB6_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB6_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB6_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = icmp ugt i32 %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK-LABEL: func8:
 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    brlenan.s %s0, %s1, .LBB7_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB7_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB7_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = fcmp ogt float %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK-LABEL: func9:
 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    brlenan.d %s0, %s1, .LBB8_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB8_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB8_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = fcmp ogt double %a, %b
   br i1 %cmp, label %on.true, label %join
 

 ; CHECK:       .LBB{{[0-9]+}}_5:
 ; CHECK-NEXT:    lea.sl %s1, 1075052544
 ; CHECK-NEXT:    brlenan.d %s0, %s1, .LBB9_1
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    lea %s0, ret@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, ret@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
-; CHECK-NEXT:    br.l .LBB9_3
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    br.l.t .LBB9_3
 ; CHECK:       .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:    or %s11, 0, %s9
 entry:
   %cmp = fcmp ogt double %a, 5.000000e+00
   br i1 %cmp, label %on.true, label %join
 
 on.true:
   %ret.val = tail call i32 @ret(i32 2)
   br label %join
 
 join:
   %r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
   ret i32 %r
 }

llvm/test/CodeGen/VE/call.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define i32 @sample_call() {
 ; CHECK-LABEL: sample_call:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, sample_add@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, sample_add@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 1, (0)1
 ; CHECK-NEXT:    or %s1, 2, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @sample_add(i32 1, i32 2)
   ret i32 %r
 }
 
 declare i32 @sample_add(i32, i32)
 
 define i32 @stack_call_int() {

 ; CHECK-NEXT:    or %s1, 2, (0)1
 ; CHECK-NEXT:    or %s2, 3, (0)1
 ; CHECK-NEXT:    or %s3, 4, (0)1
 ; CHECK-NEXT:    or %s4, 5, (0)1
 ; CHECK-NEXT:    or %s5, 6, (0)1
 ; CHECK-NEXT:    or %s6, 7, (0)1
 ; CHECK-NEXT:    or %s7, 8, (0)1
 ; CHECK-NEXT:    stl %s34, 240(, %s11)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @stack_callee_int(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10)
   ret i32 %r
 }
 
 declare i32 @stack_callee_int(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
 
 define i32 @stack_call_int_szext() {
 ; CHECK-LABEL: stack_call_int_szext:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    or %s0, -1, (0)1
 ; CHECK-NEXT:    stl %s0, 248(, %s11)
 ; CHECK-NEXT:    lea %s34, 65535
 ; CHECK-NEXT:    lea %s1, stack_callee_int_szext@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, stack_callee_int_szext@hi(, %s1)
 ; CHECK-NEXT:    lea %s1, 255
 ; CHECK-NEXT:    or %s2, 3, (0)1
 ; CHECK-NEXT:    or %s3, 4, (0)1
 ; CHECK-NEXT:    or %s4, 5, (0)1
 ; CHECK-NEXT:    or %s5, 6, (0)1
 ; CHECK-NEXT:    or %s6, 7, (0)1
 ; CHECK-NEXT:    or %s7, 8, (0)1
 ; CHECK-NEXT:    stl %s34, 240(, %s11)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call i32 @stack_callee_int_szext(i1 -1, i8 -1, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i16 -1, i8 -1)
   ret i32 %r
 }
 
 declare i32 @stack_callee_int_szext(i1 signext, i8 zeroext, i32, i32, i32, i32, i32, i32, i16 zeroext, i8 signext)
 
 define float @stack_call_float() {

 ; CHECK-NEXT:    or %s0, 0, %s1
 ; CHECK-NEXT:    or %s1, 0, %s2
 ; CHECK-NEXT:    or %s2, 0, %s3
 ; CHECK-NEXT:    or %s3, 0, %s4
 ; CHECK-NEXT:    or %s4, 0, %s5
 ; CHECK-NEXT:    or %s5, 0, %s6
 ; CHECK-NEXT:    or %s6, 0, %s7
 ; CHECK-NEXT:    or %s7, 0, %s34
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call float @stack_callee_float(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 9.0, float 10.0)
   ret float %r
 }
 
 declare float @stack_callee_float(float, float, float, float, float, float, float, float, float, float)
 
 define float @stack_call_float2(float %p0) {
 ; CHECK-LABEL: stack_call_float2:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    stu %s0, 252(, %s11)
 ; CHECK-NEXT:    lea %s1, stack_callee_float@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, stack_callee_float@hi(, %s1)
 ; CHECK-NEXT:    stu %s0, 244(, %s11)
 ; CHECK-NEXT:    or %s1, 0, %s0
 ; CHECK-NEXT:    or %s2, 0, %s0
 ; CHECK-NEXT:    or %s3, 0, %s0
 ; CHECK-NEXT:    or %s4, 0, %s0
 ; CHECK-NEXT:    or %s5, 0, %s0
 ; CHECK-NEXT:    or %s6, 0, %s0
 ; CHECK-NEXT:    or %s7, 0, %s0
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %r = tail call float @stack_callee_float(float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0, float %p0)
   ret float %r
 }
 

llvm/test/CodeGen/VE/callstruct.ll

 ; CHECK-LABEL: caller:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s0, callee@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, callee@hi(, %s0)
 ; CHECK-NEXT:    lea %s0, -8(, %s9)
 ; CHECK-NEXT:    or %s1, 3, (0)1
 ; CHECK-NEXT:    or %s2, 4, (0)1
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    ld %s0, -8(, %s9)
 ; CHECK-NEXT:    lea %s1, A@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s1, A@hi(, %s1)
 ; CHECK-NEXT:    st %s0, (, %s1)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a = alloca i64, align 8
   %a.bc = bitcast i64* %a to %struct.a*
   call void @callee(%struct.a* nonnull sret %a.bc, i32 3, i32 4)
   %a.val = load i64, i64* %a, align 8
   store i64 %a.val, i64* bitcast (%struct.a* @A to i64*), align 4
   ret void
 }
 
 declare void @callee(%struct.a* sret, i32, i32)

llvm/test/CodeGen/VE/fp_extload_truncstore.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 declare i16 @llvm.convert.to.fp16.f32(float %a)
 declare i16 @llvm.convert.to.fp16.f64(double %a)
 
 declare float @llvm.convert.from.fp16.f32(i16 %a)
 declare double @llvm.convert.from.fp16.f64(i16 %a)
 
 define float @func_i16fp32(i16* %a) {
 ; CHECK-LABEL: func_i16fp32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    ld2b.zx %s0, (, %s0)
 ; CHECK-NEXT:    lea %s1, __gnu_h2f_ieee@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_h2f_ieee@hi(, %s1)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.val = load i16, i16* %a, align 4
   %a.asd = call float @llvm.convert.from.fp16.f32(i16 %a.val)
   ret float %a.asd
 }
 
 define double @func_i16fp64(i16* %a) {
 ; CHECK-LABEL: func_i16fp64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    ld2b.zx %s0, (, %s0)
 ; CHECK-NEXT:    lea %s1, __gnu_h2f_ieee@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_h2f_ieee@hi(, %s1)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    cvt.d.s %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.val = load i16, i16* %a, align 4
   %a.asd = call double @llvm.convert.from.fp16.f64(i16 %a.val)
   ret double %a.asd
 }
 
 define float @func_fp16fp32(half* %a) {
 ; CHECK-LABEL: func_fp16fp32:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    ld2b.zx %s0, (, %s0)
 ; CHECK-NEXT:    lea %s1, __gnu_h2f_ieee@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_h2f_ieee@hi(, %s1)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.val = load half, half* %a, align 4
   %a.asd = fpext half %a.val to float
   ret float %a.asd
 }
 
 define double @func_fp16fp64(half* %a) {
 ; CHECK-LABEL: func_fp16fp64:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    ld2b.zx %s0, (, %s0)
 ; CHECK-NEXT:    lea %s1, __gnu_h2f_ieee@lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_h2f_ieee@hi(, %s1)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    cvt.d.s %s0, %s0
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.val = load half, half* %a, align 4
   %a.asd = fpext half %a.val to double
   ret double %a.asd
 }
 
 define void @func_fp32i16(i16* %fl.ptr, float %val) {
 ; CHECK-LABEL: func_fp32i16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    st %s18, 48(, %s9) # 8-byte Folded Spill
 ; CHECK-NEXT:    or %s18, 0, %s0
 ; CHECK-NEXT:    lea %s0, __gnu_f2h_ieee@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_f2h_ieee@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 0, %s1
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    st2b %s0, (, %s18)
 ; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
 ; CHECK-NEXT:    or %s11, 0, %s9
   %val.asf = call i16 @llvm.convert.to.fp16.f32(float %val)
   store i16 %val.asf, i16* %fl.ptr
   ret void
 }
 
 define half @func_fp32fp16(half* %fl.ptr, float %a) {
 ; CHECK-LABEL: func_fp32fp16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    st %s18, 48(, %s9) # 8-byte Folded Spill
 ; CHECK-NEXT:    st %s19, 56(, %s9) # 8-byte Folded Spill
 ; CHECK-NEXT:    or %s18, 0, %s0
 ; CHECK-NEXT:    lea %s0, __gnu_f2h_ieee@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_f2h_ieee@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 0, %s1
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s19, 0, %s0
 ; CHECK-NEXT:    lea %s0, __gnu_h2f_ieee@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __gnu_h2f_ieee@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 0, %s19
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    st2b %s19, (, %s18)
 ; CHECK-NEXT:    ld %s19, 56(, %s9) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
 ; CHECK-NEXT:    or %s11, 0, %s9
   %a.asd = fptrunc float %a to half
   store half %a.asd, half* %fl.ptr
   ret half %a.asd
 }

 ; CHECK-LABEL: func_fp64i16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    st %s18, 48(, %s9) # 8-byte Folded Spill
 ; CHECK-NEXT:    or %s18, 0, %s0
 ; CHECK-NEXT:    lea %s0, __truncdfhf2@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __truncdfhf2@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 0, %s1
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    st2b %s0, (, %s18)
 ; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
 ; CHECK-NEXT:    or %s11, 0, %s9
   %val.asf = call i16 @llvm.convert.to.fp16.f64(double %val)
   store i16 %val.asf, i16* %fl.ptr
   ret void
 }
 
 define void @func_fp64fp16(half* %fl.ptr, double %val) {
 ; CHECK-LABEL: func_fp64fp16:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    st %s18, 48(, %s9) # 8-byte Folded Spill
 ; CHECK-NEXT:    or %s18, 0, %s0
 ; CHECK-NEXT:    lea %s0, __truncdfhf2@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, __truncdfhf2@hi(, %s0)
 ; CHECK-NEXT:    or %s0, 0, %s1
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    st2b %s0, (, %s18)
 ; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
 ; CHECK-NEXT:    or %s11, 0, %s9
   %val.asf = fptrunc double %val to half
   store half %val.asf, half* %fl.ptr
   ret void
 }
 

llvm/test/CodeGen/VE/pic_access_static_data.ll

 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s0, src@gotoff_hi(, %s0)
 ; CHECK-NEXT:    or %s1, 1, (0)1
 ; CHECK-NEXT:    st1b %s1, (%s0, %s15)
 ; CHECK-NEXT:    lea %s12, func@plt_lo(-24)
 ; CHECK-NEXT:    and %s12, %s12, (32)0
 ; CHECK-NEXT:    sic %s16
 ; CHECK-NEXT:    lea.sl %s12, func@plt_hi(%s16, %s12)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    lea %s0, dst@gotoff_lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s0, dst@gotoff_hi(, %s0)
 ; CHECK-NEXT:    ldl.sx %s1, (%s0, %s15)
 ; CHECK-NEXT:    stl %s1, 184(, %s11)
 ; CHECK-NEXT:    lea %s0, .L.str@gotoff_lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s0, .L.str@gotoff_hi(, %s0)
 ; CHECK-NEXT:    adds.l %s0, %s15, %s0
 ; CHECK-NEXT:    lea %s12, printf@plt_lo(-24)
 ; CHECK-NEXT:    and %s12, %s12, (32)0
 ; CHECK-NEXT:    sic %s16
 ; CHECK-NEXT:    lea.sl %s12, printf@plt_hi(%s16, %s12)
 ; CHECK-NEXT:    st %s0, 176(, %s11)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s0, 0, (0)1
 ; CHECK-NEXT:    or %s11, 0, %s9
   store i1 true, i1* @src, align 4
   tail call void @func()
   %1 = load i32, i32* @dst, align 4
   %2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @.str, i64 0, i64 0), i32 %1)
   ret i32 0
 }
 
 declare i32 @printf(i8* nocapture readonly, ...)

llvm/test/CodeGen/VE/pic_func_call.ll

 ; RUN: llc -relocation-model=pic < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define void @func() {
 ; CHECK-LABEL: func:
 ; CHECK:       .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
 ; CHECK-NEXT:    and %s15, %s15, (32)0
 ; CHECK-NEXT:    sic %s16
 ; CHECK-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
 ; CHECK-NEXT:    lea %s12, function@plt_lo(-24)
 ; CHECK-NEXT:    and %s12, %s12, (32)0
 ; CHECK-NEXT:    sic %s16
 ; CHECK-NEXT:    lea.sl %s12, function@plt_hi(%s16, %s12)
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
 
   call void bitcast (void (...)* @function to void ()*)()
   ret void
 }
 
 declare void @function(...)

llvm/test/CodeGen/VE/pic_indirect_func_call.ll

 ; CHECK-NEXT:    lea.sl %s0, function@got_hi(, %s0)
 ; CHECK-NEXT:    ld %s0, (%s0, %s15)
 ; CHECK-NEXT:    lea %s1, ptr@got_lo
 ; CHECK-NEXT:    and %s1, %s1, (32)0
 ; CHECK-NEXT:    lea.sl %s1, ptr@got_hi(, %s1)
 ; CHECK-NEXT:    ld %s1, (%s1, %s15)
 ; CHECK-NEXT:    st %s0, (, %s1)
 ; CHECK-NEXT:    or %s12, 0, %s0
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s11, 0, %s9
 
   store void (...)* @function, void (...)** @ptr, align 8
   %1 = load void (...)*, void (...)** @ptr, align 8
   %2 = bitcast void (...)* %1 to void ()*
   call void %2()
   ret void
 }
 
 declare void @function(...)

llvm/test/CodeGen/VE/simple_prologue_epilogue.ll

 ; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
 
 define void @func() {
 ; CHECK-LABEL: func:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  st %s9, (, %s11)
 ; CHECK-NEXT:  st %s10, 8(, %s11)
 ; CHECK-NEXT:  st %s15, 24(, %s11)
 ; CHECK-NEXT:  st %s16, 32(, %s11)
 ; CHECK-NEXT:  or %s9, 0, %s11
 ; CHECK-NEXT:  lea %s13, -176
 ; CHECK-NEXT:  and %s13, %s13, (32)0
 ; CHECK-NEXT:  lea.sl %s11, -1(%s13, %s11)
-; CHECK-NEXT:  brge.l %s11, %s8, .LBB0_2
+; CHECK-NEXT:  brge.l.t %s11, %s8, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:  ld %s61, 24(, %s14)
 ; CHECK-NEXT:  or %s62, 0, %s0
 ; CHECK-NEXT:  lea %s63, 315
 ; CHECK-NEXT:  shm.l %s63, (%s61)
 ; CHECK-NEXT:  shm.l %s8, 8(%s61)
 ; CHECK-NEXT:  shm.l %s11, 16(%s61)
 ; CHECK-NEXT:  monc
 ; CHECK-NEXT:  or %s0, 0, %s62
 ; CHECK-NEXT: .LBB0_2:
 ; CHECK-NEXT:  or %s11, 0, %s9
 ; CHECK-NEXT:  ld %s16, 32(, %s11)
 ; CHECK-NEXT:  ld %s15, 24(, %s11)
 ; CHECK-NEXT:  ld %s10, 8(, %s11)
 ; CHECK-NEXT:  ld %s9, (, %s11)
-; CHECK-NEXT:  b.l (,%lr)
+; CHECK-NEXT:  b.l.t (, %s10)
   ret void
 }
 
 define i64 @func1(i64) {
 ; CHECK-LABEL: func1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  st %s9, (, %s11)
 ; CHECK-NEXT:  st %s10, 8(, %s11)
 ; CHECK-NEXT:  st %s15, 24(, %s11)
 ; CHECK-NEXT:  st %s16, 32(, %s11)
 ; CHECK-NEXT:  or %s9, 0, %s11
 ; CHECK-NEXT:  lea %s13, -176
 ; CHECK-NEXT:  and %s13, %s13, (32)0
 ; CHECK-NEXT:  lea.sl %s11, -1(%s13, %s11)
-; CHECK-NEXT:  brge.l %s11, %s8, .LBB1_2
+; CHECK-NEXT:  brge.l.t %s11, %s8, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:  ld %s61, 24(, %s14)
 ; CHECK-NEXT:  or %s62, 0, %s0
 ; CHECK-NEXT:  lea %s63, 315
 ; CHECK-NEXT:  shm.l %s63, (%s61)
 ; CHECK-NEXT:  shm.l %s8, 8(%s61)
 ; CHECK-NEXT:  shm.l %s11, 16(%s61)
 ; CHECK-NEXT:  monc
 ; CHECK-NEXT:  or %s0, 0, %s62
 ; CHECK-NEXT: .LBB1_2:
 ; CHECK-NEXT:  or %s11, 0, %s9
 ; CHECK-NEXT:  ld %s16, 32(, %s11)
 ; CHECK-NEXT:  ld %s15, 24(, %s11)
 ; CHECK-NEXT:  ld %s10, 8(, %s11)
 ; CHECK-NEXT:  ld %s9, (, %s11)
-; CHECK-NEXT:  b.l (,%lr)
+; CHECK-NEXT:  b.l.t (, %s10)
   ret i64 %0
 }
 
 define i64 @func2(i64, i64, i64, i64, i64) {
 ; CHECK-LABEL: func2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:  st %s9, (, %s11)
 ; CHECK-NEXT:  st %s10, 8(, %s11)
 ; CHECK-NEXT:  st %s15, 24(, %s11)
 ; CHECK-NEXT:  st %s16, 32(, %s11)
 ; CHECK-NEXT:  or %s9, 0, %s11
 ; CHECK-NEXT:  lea %s13, -176
 ; CHECK-NEXT:  and %s13, %s13, (32)0
 ; CHECK-NEXT:  lea.sl %s11, -1(%s13, %s11)
-; CHECK-NEXT:  brge.l %s11, %s8, .LBB2_2
+; CHECK-NEXT:  brge.l.t %s11, %s8, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:  ld %s61, 24(, %s14)
 ; CHECK-NEXT:  or %s62, 0, %s0
 ; CHECK-NEXT:  lea %s63, 315
 ; CHECK-NEXT:  shm.l %s63, (%s61)
 ; CHECK-NEXT:  shm.l %s8, 8(%s61)
 ; CHECK-NEXT:  shm.l %s11, 16(%s61)
 ; CHECK-NEXT:  monc
 ; CHECK-NEXT:  or %s0, 0, %s62
 ; CHECK-NEXT: .LBB2_2:
 ; CHECK-NEXT:  or %s0, 0, %s4
 ; CHECK-NEXT:  or %s11, 0, %s9
 ; CHECK-NEXT:  ld %s16, 32(, %s11)
 ; CHECK-NEXT:  ld %s15, 24(, %s11)
 ; CHECK-NEXT:  ld %s10, 8(, %s11)
 ; CHECK-NEXT:  ld %s9, (, %s11)
-; CHECK-NEXT:  b.l (,%lr)
+; CHECK-NEXT:  b.l.t (, %s10)
   ret i64 %4
 }

llvm/test/CodeGen/VE/va_caller.ll

 ; CHECK-NEXT:    or %s18, 0, (0)1
 ; CHECK-NEXT:    lea %s0, func@lo
 ; CHECK-NEXT:    and %s0, %s0, (32)0
 ; CHECK-NEXT:    lea.sl %s12, func@hi(, %s0)
 ; CHECK-NEXT:    lea.sl %s0, 1086324736
 ; CHECK-NEXT:    stl %s18, 176(, %s11)
 ; CHECK-NEXT:    or %s6, 0, %s0
 ; CHECK-NEXT:    or %s0, 0, %s18
-; CHECK-NEXT:    bsic %lr, (,%s12)
+; CHECK-NEXT:    bsic %s10, (, %s12)
 ; CHECK-NEXT:    or %s0, 0, %s18
 ; CHECK-NEXT:    ld %s18, 48(, %s9) # 8-byte Folded Reload
 ; CHECK-NEXT:    or %s11, 0, %s9
   call i32 (i32, ...) @func(i32 0, i16 1, i8 2, i32 3, i16 4, i8 5, float 6.0, i8* null, i64 8, double 9.0, i128 10, i128 11)
   ret i32 0
 }