PowerPC: Treat llvm.fma.f* intrinsic as using CTR with SPE

[jhibbits]

Summary

The SPE doesn't have a 'fma' instruction, so the intrinsic becomes a
libcall. It really should become an expansion to two instructions, but
for some reason the compiler doesn't think that's as optimal as a
branch. Since this lowering is done after CTR is allocated for loops,
tell the optimizer that CTR may be used in this case. This prevents a
"Invalid PPC CTR loop!" assertion in the case that a fma() function call
is used in a C/C++ file, and clang converts it into an intrinsic.

[shchenz]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

324

In PPCTargetLowering::PPCTargetLowering, We already have

if (Subtarget.hasSPE()) {
   setOperationAction(ISD::FMA  , MVT::f64, Expand);
   setOperationAction(ISD::FMA  , MVT::f32, Expand);
}

And there is a hook function TLI->isOperationLegalOrCustom(Opcode, EVTy) at line 415. I think better to use that function to check if one operation with a type is legal or not, similar with following Intrinsic::sqrt?

llvm/test/CodeGen/PowerPC/spe.ll

1357

Accidentally delete?

[jhibbits]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

324

I'm surprised I missed that, quite the oversight. Yes, that test below is much preferred, I was afraid I might need to play whack-a-mole on this, and wondering why that wasn't the case except for FMA. Fixing it to the better way.

llvm/test/CodeGen/PowerPC/spe.ll

1357

Yeah. a botched rebase sorting my local commits.

[jhibbits]

Address feedback from @shchenz. Much better!

Questionable on the sorting where I put the intrinsic check, there doesn't
appear to be any kind of sort order, so hope it's fine.

[shchenz]

LGTM

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

if (CallInst *CI = dyn_cast<CallInst>(J)) {
           case Intrinsic::cos:
             return true;
           case Intrinsic::copysign:
             if (CI->getArgOperand(0)->getType()->getScalarType()->
                 isPPC_FP128Ty())
               return true;
             else
               continue; // ISD::FCOPYSIGN is never a library call.
+          case Intrinsic::fma:                Opcode = ISD::FMA;        break;
           case Intrinsic::sqrt:               Opcode = ISD::FSQRT;      break;
           case Intrinsic::floor:              Opcode = ISD::FFLOOR;     break;
           case Intrinsic::ceil:               Opcode = ISD::FCEIL;      break;
           case Intrinsic::trunc:              Opcode = ISD::FTRUNC;     break;
           case Intrinsic::rint:               Opcode = ISD::FRINT;      break;
           case Intrinsic::lrint:              Opcode = ISD::LRINT;      break;
           case Intrinsic::llrint:             Opcode = ISD::LLRINT;     break;
           case Intrinsic::nearbyint:          Opcode = ISD::FNEARBYINT; break;
           case Intrinsic::round:              Opcode = ISD::FROUND;     break;
           case Intrinsic::lround:             Opcode = ISD::LROUND;     break;

llvm/test/CodeGen/PowerPC/spe.ll

entry:
   call void @test_func2()
   %3 = bitcast [11 x i32]* %v2 to i8*
   call void @test_memset(i8* align 4 %3, i8 0, i32 20, i1 true)
   br label %return
 
 return:
   ret double %1
 
 }
+
+define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 {
+; CHECK-LABEL: test_fma:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    stw 0, 4(1)
+; CHECK-NEXT:    stwu 1, -48(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    .cfi_offset lr, 4
+; CHECK-NEXT:    .cfi_offset r29, -12
+; CHECK-NEXT:    .cfi_offset r30, -8
+; CHECK-NEXT:    .cfi_offset r29, -40
+; CHECK-NEXT:    .cfi_offset r30, -32
+; CHECK-NEXT:    cmpwi 3, 1
+; CHECK-NEXT:    stw 29, 36(1) # 4-byte Folded Spill
+; CHECK-NEXT:    stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
+; CHECK-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
+; CHECK-NEXT:    blt 0, .LBB57_3
+; CHECK-NEXT:  # %bb.1: # %for.body.preheader
+; CHECK-NEXT:    mr 30, 3
+; CHECK-NEXT:    li 29, 0
+; CHECK-NEXT:    # implicit-def: $r5
+; CHECK-NEXT:  .LBB57_2: # %for.body
+; CHECK-NEXT:    #
+; CHECK-NEXT:    efscfsi 3, 29
+; CHECK-NEXT:    mr 4, 3
+; CHECK-NEXT:    bl fmaf
+; CHECK-NEXT:    addi 29, 29, 1
+; CHECK-NEXT:    cmplw 30, 29
+; CHECK-NEXT:    mr 5, 3
+; CHECK-NEXT:    bne 0, .LBB57_2
+; CHECK-NEXT:    b .LBB57_4
+; CHECK-NEXT:  .LBB57_3:
+; CHECK-NEXT:    # implicit-def: $r5
+; CHECK-NEXT:  .LBB57_4: # %for.cond.cleanup
+; CHECK-NEXT:    evldd 30, 16(1) # 8-byte Folded Reload
+; CHECK-NEXT:    evldd 29, 8(1) # 8-byte Folded Reload
+; CHECK-NEXT:    mr 3, 5
+; CHECK-NEXT:    lwz 30, 40(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 29, 36(1) # 4-byte Folded Reload
+; CHECK-NEXT:    lwz 0, 52(1)
+; CHECK-NEXT:    addi 1, 1, 48
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+entry:
+  %cmp8 = icmp sgt i32 %d, 0
+  br i1 %cmp8, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:                                 ; preds = %for.body, %entry
+  %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ]
+  ret float %e.0.lcssa
+
+for.body:                                         ; preds = %for.body, %entry
+  %f.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %e.09 = phi float [ %0, %for.body ], [ undef, %entry ]
+  %conv = sitofp i32 %f.010 to float
+  %0 = tail call float @llvm.fma.f32(float %conv, float %conv, float %e.09)
+  %inc = add nuw nsw i32 %f.010, 1
+  %exitcond = icmp eq i32 %inc, %d
+  br i1 %exitcond, label %for.cond.cleanup, label %for.body
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare float @llvm.fma.f32(float, float, float) #1
+
+attributes #1 = { nounwind readnone speculatable willreturn }