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Differential D77992

[AMDGPU] Don't assert on partial exec copy
ClosedPublic

Authored by kerbowa on Apr 12 2020, 8:46 PM.

Details

Reviewers
rampitec
Commits
rGeab9a4f1192a: [AMDGPU] Don't assert on partial exec copy
Summary

After Machine CSE and coalescing we can end up with copies of exec to
subregister SGPRs.

Diff Detail

Event Timeline

kerbowa created this revision.Apr 12 2020, 8:46 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 12 2020, 8:46 PM
Herald added subscribers: llvm-commits, hiraditya, t-tye and 8 others. · View Herald Transcript
rampitec accepted this revision.Apr 12 2020, 9:00 PM

LGTM

This revision is now accepted and ready to land.Apr 12 2020, 9:00 PM
Harbormaster completed remote builds in B52896: Diff 256912.Apr 12 2020, 9:23 PM
Closed by commit rGeab9a4f1192a: [AMDGPU] Don't assert on partial exec copy (authored by kerbowa). · Explain WhyApr 12 2020, 9:23 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
4 lines
test/
CodeGen/
AMDGPU/
22 lines

Diff 256916

llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() { FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
return new SIOptimizeExecMaskingPreRA(); return new SIOptimizeExecMaskingPreRA();
} }
static bool isFullExecCopy(const MachineInstr& MI, const GCNSubtarget& ST) { static bool isFullExecCopy(const MachineInstr& MI, const GCNSubtarget& ST) {
unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
if (MI.isCopy() && MI.getOperand(1).getReg() == Exec) { if (MI.isFullCopy() && MI.getOperand(1).getReg() == Exec)
assert(MI.isFullCopy());
return true; return true;
}
return false; return false;
} }
// Optimize sequence // Optimize sequence
// %sel = V_CNDMASK_B32_e64 0, 1, %cc // %sel = V_CNDMASK_B32_e64 0, 1, %cc
// %cmp = V_CMP_NE_U32 1, %1 // %cmp = V_CMP_NE_U32 1, %1
// $vcc = S_AND_B64 $exec, %cmp // $vcc = S_AND_B64 $exec, %cmp
▲ Show 20 Lines • Show All 246 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines bb.0:
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
S_CBRANCH_VCCZ %bb.1, implicit $vcc S_CBRANCH_VCCZ %bb.1, implicit $vcc
bb.1: bb.1:
... ...
# Don't crash on exec copy to SGPR subregister.
---
name: exec_copy_to_subreg
tracksRegLiveness: true
body: |
; GCN-LABEL: name: exec_copy_to_subreg
; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000)
; GCN: dead undef %0.sub0:sreg_256 = COPY $exec
; GCN: dead %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %2:sreg_64_xexec, implicit $exec
; GCN: S_BRANCH %bb.1
; GCN: bb.1:
bb.0:
undef %0.sub0:sreg_256 = COPY $exec
%2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec
S_BRANCH %bb.1
bb.1:
...