[AArch64] Don't expand memcmp in strict align mode.

[efriedma]

Summary

7aecf232 fixed the bug where we would miscompile, but we still generate a crazy amount of code. Turn off the expansion until someone implements an appropriate heuristic.

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

if (ValTy->isVectorTy() && ISD == ISD::SELECT) {
     }
   }
   return BaseT::getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
 }
 
 AArch64TTIImpl::TTI::MemCmpExpansionOptions
 AArch64TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
   TTI::MemCmpExpansionOptions Options;
-  Options.AllowOverlappingLoads = !ST->requiresStrictAlign();
+  if (ST->requiresStrictAlign()) {
+    // TODO: Add cost modeling for strict align. Misaligned loads expand to
+    // a bunch of instructions when strict align is enabled.
+    return Options;
+  }
+  Options.AllowOverlappingLoads = true;
   Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
   Options.NumLoadsPerBlock = Options.MaxNumLoads;
   // TODO: Though vector loads usually perform well on AArch64, in some targets
   // they may wake up the FP unit, which raises the power consumption.  Perhaps
   // they could be used with no holds barred (-O3).
   Options.LoadSizes = {8, 4, 2, 1};
   return Options;
 }

llvm/test/CodeGen/AArch64/bcmp-inline-small.ll

 ; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu                     | FileCheck %s --check-prefixes=CHECK,CHECKN
 ; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu -mattr=strict-align | FileCheck %s --check-prefixes=CHECK,CHECKS
 
 declare i32 @bcmp(i8*, i8*, i64) nounwind readonly
 declare i32 @memcmp(i8*, i8*, i64) nounwind readonly
 
 define i1 @test_b2(i8* %s1, i8* %s2) {
 entry:
   %bcmp = call i32 @bcmp(i8* %s1, i8* %s2, i64 15)
   %ret = icmp eq i32 %bcmp, 0
   ret i1 %ret
 
 ; CHECK-LABEL: test_b2:
-; CHECK-NOT:   bl bcmp
+; CHECKN-NOT:  bl bcmp
 ; CHECKN:      ldr  x
 ; CHECKN-NEXT: ldr  x
 ; CHECKN-NEXT: ldur x
 ; CHECKN-NEXT: ldur x
-; CHECKS-COUNT-30: ldrb w
+; CHECKS: bl bcmp
 }
 
 define i1 @test_b2_align8(i8* align 8 %s1, i8* align 8 %s2) {
 entry:
   %bcmp = call i32 @bcmp(i8* %s1, i8* %s2, i64 15)
   %ret = icmp eq i32 %bcmp, 0
   ret i1 %ret
 
 ; CHECK-LABEL: test_b2_align8:
-; CHECK-NOT:   bl bcmp
+; CHECKN-NOT:  bl bcmp
 ; CHECKN:      ldr  x
 ; CHECKN-NEXT: ldr  x
 ; CHECKN-NEXT: ldur x
 ; CHECKN-NEXT: ldur x
-; CHECKS:      ldr  x
-; CHECKS-NEXT: ldr  x
-; CHECKS-NEXT: ldr  w
-; CHECKS-NEXT: ldr  w
-; CHECKS-NEXT: ldrh  w
-; CHECKS-NEXT: ldrh  w
-; CHECKS-NEXT: ldrb  w
-; CHECKS-NEXT: ldrb  w
+; TODO: Four loads should be within the limit, but the heuristic isn't implemented.
+; CHECKS: bl bcmp
 }
 
 define i1 @test_bs(i8* %s1, i8* %s2) optsize {
 entry:
   %memcmp = call i32 @memcmp(i8* %s1, i8* %s2, i64 31)
   %ret = icmp eq i32 %memcmp, 0
   ret i1 %ret