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Differential D77092

[SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.
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Authored by craig.topper on Mar 30 2020, 1:58 PM.

Details

Reviewers
aqjune
spatel
lebedev.ri
Commits
rG2a07221cf302: [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE…

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Event Timeline

craig.topper created this revision.Mar 30 2020, 1:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2020, 1:58 PM
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Harbormaster completed remote builds in B51024: Diff 253697.Mar 30 2020, 2:44 PM
aqjune accepted this revision.Mar 30 2020, 6:18 PM

LGTM

This revision is now accepted and ready to land.Mar 30 2020, 6:18 PM
Closed by commit rG2a07221cf302: [SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE… (authored by craig.topper). · Explain WhyMar 30 2020, 11:25 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
3 lines

Diff 253697

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===// //===- SelectionDAG.cpp - Implement the SelectionDAG data structures ------===//
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// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 4,536 Lines • ▼ Show 20 Lines if (BV->isConstant()) {
return Fold; return Fold;
} }
} }
} }
} }
unsigned OpOpcode = Operand.getNode()->getOpcode(); unsigned OpOpcode = Operand.getNode()->getOpcode();
switch (Opcode) { switch (Opcode) {
case ISD::FREEZE:
assert(VT == Operand.getValueType() && "Unexpected VT!");
break;
case ISD::TokenFactor: case ISD::TokenFactor:
case ISD::MERGE_VALUES: case ISD::MERGE_VALUES:
case ISD::CONCAT_VECTORS: case ISD::CONCAT_VECTORS:
return Operand; // Factor, merge or concat of one node? No need. return Operand; // Factor, merge or concat of one node? No need.
case ISD::BUILD_VECTOR: { case ISD::BUILD_VECTOR: {
// Attempt to simplify BUILD_VECTOR. // Attempt to simplify BUILD_VECTOR.
SDValue Ops[] = {Operand}; SDValue Ops[] = {Operand};
if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this)) if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
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