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[SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.
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Authored by craig.topper on Mar 30 2020, 1:58 PM.

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LGTM

This revision is now accepted and ready to land.Mar 30 2020, 6:18 PM

This revision was automatically updated to reflect the committed changes.

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llvm/

lib/

CodeGen/

SelectionDAG/

3 lines

Show First 20 Lines • Show All 4,544 Lines • ▼ Show 20 Lines	if (BV->isConstant()) {
return Fold;		return Fold;
}		}
}		}
}		}
}		}

unsigned OpOpcode = Operand.getNode()->getOpcode();		unsigned OpOpcode = Operand.getNode()->getOpcode();
switch (Opcode) {		switch (Opcode) {
		case ISD::FREEZE:
		assert(VT == Operand.getValueType() && "Unexpected VT!");
		break;
case ISD::TokenFactor:		case ISD::TokenFactor:
case ISD::MERGE_VALUES:		case ISD::MERGE_VALUES:
case ISD::CONCAT_VECTORS:		case ISD::CONCAT_VECTORS:
return Operand; // Factor, merge or concat of one node? No need.		return Operand; // Factor, merge or concat of one node? No need.
case ISD::BUILD_VECTOR: {		case ISD::BUILD_VECTOR: {
// Attempt to simplify BUILD_VECTOR.		// Attempt to simplify BUILD_VECTOR.
SDValue Ops[] = {Operand};		SDValue Ops[] = {Operand};
if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))		if (SDValue V = FoldBUILD_VECTOR(DL, VT, Ops, *this))
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