AMDGPU: Don't handle kernarg.segment.ptr in functions

[arsenm]

Summary

Just lower this to null. Pass implicitarg.ptr in its place in the
argument list.

[b-sumner]

I'm not aware of any valid explicit uses of this intrinsic by library or developer code, so this seems fine to me.

[rampitec]

A trap would be better, we can easily spot it.

[arsenm]

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

A trap isn’t particularly different from the null dereference if you try to actually use it. I was leaning more towards a compile time error

[rampitec]

In D76107#1920749, @arsenm wrote:

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

A trap isn’t particularly different from the null dereference if you try to actually use it. I was leaning more towards a compile time error

It is actually very different. A null pointer dereference means debugging, tracking the pointer, analyzing IR step by step until you see why was null emitted. A trap on the contrary is immediately visible in the ISA dump and immediately triggers the alarm, that compiler have spotted the code which should never been executed.

[arsenm]

In D76107#1920799, @rampitec wrote:

In D76107#1920749, @arsenm wrote:

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

A trap isn’t particularly different from the null dereference if you try to actually use it. I was leaning more towards a compile time error

It is actually very different. A null pointer dereference means debugging, tracking the pointer, analyzing IR step by step until you see why was null emitted. A trap on the contrary is immediately visible in the ISA dump and immediately triggers the alarm, that compiler have spotted the code which should never been executed.

The trap adds extra complexity to the implementation since now the queue ptr needs to be passed to the function. This should probably be considered a backend internal intrinsic now, so I'm not sure it's worth the effort

[rampitec]

In D76107#1920749, @arsenm wrote:

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

A trap isn’t particularly different from the null dereference if you try to actually use it. I was leaning more towards a compile time error

It is actually very different. A null pointer dereference means debugging, tracking the pointer, analyzing IR step by step until you see why was null emitted. A trap on the contrary is immediately visible in the ISA dump and immediately triggers the alarm, that compiler have spotted the code which should never been executed.

In D76107#1921570, @arsenm wrote:

In D76107#1920799, @rampitec wrote:

In D76107#1920749, @arsenm wrote:

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

In D76107#1920704, @rampitec wrote:

A trap would be better, we can easily spot it.

A trap isn’t particularly different from the null dereference if you try to actually use it. I was leaning more towards a compile time error

It is actually very different. A null pointer dereference means debugging, tracking the pointer, analyzing IR step by step until you see why was null emitted. A trap on the contrary is immediately visible in the ISA dump and immediately triggers the alarm, that compiler have spotted the code which should never been executed.

The trap adds extra complexity to the implementation since now the queue ptr needs to be passed to the function. This should probably be considered a backend internal intrinsic now, so I'm not sure it's worth the effort

Sigh. OK, let's hope we will never have to debug it.

[arsenm]

bb8622094d77417c629e45fc9964d0b699019f22

llvm/lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp

 static void copyFeaturesToFunction(Function &Parent, const Function &Callee,
                                    bool &NeedQueuePtr) {
   // X ids unnecessarily propagated to kernels.
   static constexpr StringLiteral AttrNames[] = {
       "amdgpu-work-item-id-x",      "amdgpu-work-item-id-y",
       "amdgpu-work-item-id-z",      "amdgpu-work-group-id-x",
       "amdgpu-work-group-id-y",     "amdgpu-work-group-id-z",
       "amdgpu-dispatch-ptr",        "amdgpu-dispatch-id",
-      "amdgpu-kernarg-segment-ptr", "amdgpu-implicitarg-ptr"};
+      "amdgpu-implicitarg-ptr"};
 
   if (handleAttr(Parent, Callee, "amdgpu-queue-ptr"))
     NeedQueuePtr = true;
 
   for (StringRef AttrName : AttrNames)
     handleAttr(Parent, Callee, AttrName);
 }
 
for (Instruction &I : BB) {
 
         Intrinsic::ID IID = Callee->getIntrinsicID();
         if (IID == Intrinsic::not_intrinsic) {
           HaveCall = true;
           copyFeaturesToFunction(F, *Callee, NeedQueuePtr);
           Changed = true;
         } else {
           bool NonKernelOnly = false;
-          StringRef AttrName = intrinsicToAttrName(IID,
-                                                   NonKernelOnly, NeedQueuePtr);
+
+          if (!IsFunc && IID == Intrinsic::amdgcn_kernarg_segment_ptr) {
+            F.addFnAttr("amdgpu-kernarg-segment-ptr");
+          } else {
+            StringRef AttrName = intrinsicToAttrName(IID, NonKernelOnly,
+                                                     NeedQueuePtr);
             if (!AttrName.empty() && (IsFunc || !NonKernelOnly)) {
               F.addFnAttr(AttrName);
               Changed = true;
             }
           }
         }
+      }
 
       if (NeedQueuePtr || (!IsFunc && HasApertureRegs))
         continue;
 
       if (const AddrSpaceCastInst *ASC = dyn_cast<AddrSpaceCastInst>(&I)) {
         if (!HasApertureRegs && castRequiresQueuePtr(ASC)) {
           NeedQueuePtr = true;
           continue;

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

if (MachineInstr *BrCond = verifyCFIntrinsic(MI, MRI, Br)) {
       BrCond->eraseFromParent();
       MRI.setRegClass(Reg, TRI->getWaveMaskRegClass());
       return true;
     }
 
     return false;
   }
   case Intrinsic::amdgcn_kernarg_segment_ptr:
+    if (!AMDGPU::isKernel(B.getMF().getFunction().getCallingConv())) {
+      B.setInstr(MI);
+      // This only makes sense to call in a kernel, so just lower to null.
+      B.buildConstant(MI.getOperand(0).getReg(), 0);
+      MI.eraseFromParent();
+      return true;
+    }
+
     return legalizePreloadedArgIntrin(
       MI, MRI, B, AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
   case Intrinsic::amdgcn_implicitarg_ptr:
     return legalizeImplicitArgPtr(MI, MRI, B);
   case Intrinsic::amdgcn_workitem_id_x:
     return legalizePreloadedArgIntrin(MI, MRI, B,
                                       AMDGPUFunctionArgInfo::WORKITEM_ID_X);
   case Intrinsic::amdgcn_workitem_id_y:

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

void SITargetLowering::allocateSpecialInputSGPRs(
   // TODO: Unify handling with private memory pointers.
 
   if (Info.hasDispatchPtr())
     ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
 
   if (Info.hasQueuePtr())
     ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
 
-  if (Info.hasKernargSegmentPtr())
-    ArgInfo.KernargSegmentPtr = allocateSGPR64Input(CCInfo);
+  // Implicit arg ptr takes the place of the kernarg segment pointer. This is a
+  // constant offset from the kernarg segment.
+  if (Info.hasImplicitArgPtr())
+    ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
 
   if (Info.hasDispatchID())
     ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
 
   // flat_scratch_init is not applicable for non-kernel functions.
 
   if (Info.hasWorkGroupIDX())
     ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
 
   if (Info.hasWorkGroupIDY())
     ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
 
   if (Info.hasWorkGroupIDZ())
     ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
-
-  if (Info.hasImplicitArgPtr())
-    ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
 }
 
 // Allocate special inputs passed in user SGPRs.
 void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
                                             MachineFunction &MF,
                                             const SIRegisterInfo &TRI,
                                             SIMachineFunctionInfo &Info) const {
   if (Info.hasImplicitBufferPtr()) {
void SITargetLowering::passSpecialInputs(
   const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
 
   // TODO: Unify with private memory register handling. This is complicated by
   // the fact that at least in kernels, the input argument is not necessarily
   // in the same location as the input.
   AMDGPUFunctionArgInfo::PreloadedValue InputRegs[] = {
     AMDGPUFunctionArgInfo::DISPATCH_PTR,
     AMDGPUFunctionArgInfo::QUEUE_PTR,
-    AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR,
+    AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR,
     AMDGPUFunctionArgInfo::DISPATCH_ID,
     AMDGPUFunctionArgInfo::WORKGROUP_ID_X,
     AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,
-    AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,
-    AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
+    AMDGPUFunctionArgInfo::WORKGROUP_ID_Z
   };
 
   for (auto InputID : InputRegs) {
     const ArgDescriptor *OutgoingArg;
     const TargetRegisterClass *ArgRC;
 
     std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
     if (!OutgoingArg)
SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   }
   case Intrinsic::amdgcn_implicitarg_ptr: {
     if (MFI->isEntryFunction())
       return getImplicitArgPtr(DAG, DL);
     return getPreloadedValue(DAG, *MFI, VT,
                              AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
   }
   case Intrinsic::amdgcn_kernarg_segment_ptr: {
+    if (!AMDGPU::isKernel(MF.getFunction().getCallingConv())) {
+      // This only makes sense to call in a kernel, so just lower to null.
+      return DAG.getConstant(0, DL, VT);
+    }
+
     return getPreloadedValue(DAG, *MFI, VT,
                              AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
   }
   case Intrinsic::amdgcn_dispatch_id: {
     return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::DISPATCH_ID);
   }
   case Intrinsic::amdgcn_rcp:
     return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll

 define amdgpu_kernel void @opencl_test_implicit_alignment_no_explicit_kernargs_round_up() #3 {
   %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %val = load volatile i32, i32 addrspace(4)* %arg.ptr
   store volatile i32 %val, i32 addrspace(1)* null
   ret void
 }
 
+; ALL-LABEL: {{^}}func_kernarg_segment_ptr:
+; ALL: s_mov_b32 [[S_LO:s[0-9]+]], 0{{$}}
+; ALL: s_mov_b32 [[S_HI:s[0-9]+]], 0{{$}}
+; ALL: v_mov_b32_e32 v0, [[S_LO]]{{$}}
+; ALL: v_mov_b32_e32 v1, [[S_HI]]{{$}}
+define i8 addrspace(4)* @func_kernarg_segment_ptr() {
+  %ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
+  ret i8 addrspace(4)* %ptr
+}
+
 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { nounwind }
 attributes #2 = { nounwind "amdgpu-implicitarg-num-bytes"="48" }
 attributes #3 = { nounwind "amdgpu-implicitarg-num-bytes"="38" }

llvm/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll

 
 ; HSA: define void @use_kernarg_segment_ptr() #14 {
 define void @use_kernarg_segment_ptr() #1 {
   %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
   store volatile i8 addrspace(4)* %kernarg.segment.ptr, i8 addrspace(4)* addrspace(1)* undef
   ret void
 }
 
-; HSA: define void @func_indirect_use_kernarg_segment_ptr() #14 {
+; HSA: define void @func_indirect_use_kernarg_segment_ptr() #11 {
 define void @func_indirect_use_kernarg_segment_ptr() #1 {
   call void @use_kernarg_segment_ptr()
   ret void
 }
 
 ; HSA: define amdgpu_kernel void @kern_use_implicitarg_ptr() #15 {
 define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 {
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()

llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

 ; CIVI-NOT: s[4:5]
 ; CIVI-NOT: s4
 ; CIVI-NOT: s5
 define amdgpu_kernel void @kern_indirect_use_queue_ptr_addrspacecast(i32) #1 {
   call void @use_queue_ptr_addrspacecast()
   ret void
 }
 
+; Not really supported in callable functions.
 ; GCN-LABEL: {{^}}use_kernarg_segment_ptr:
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s4
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s5
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+; GCN: s_mov_b64 [[PTR:s\[[0-9]+:[0-9]+\]]], 0{{$}}
+; GCN: s_load_dword s{{[0-9]+}}, [[PTR]], 0x0{{$}}
 define hidden void @use_kernarg_segment_ptr() #1 {
   %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
   %header_ptr = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
   %value = load volatile i32, i32 addrspace(4)* %header_ptr
   ret void
 }
 
 ; GCN-LABEL: {{^}}kern_indirect_use_kernarg_segment_ptr:
 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
-; GCN-NOT: s[4:5]
-; GCN-NOT: s4
-; GCN-NOT: s5
-; GCN: s_swappc_b64
 define amdgpu_kernel void @kern_indirect_use_kernarg_segment_ptr(i32) #1 {
   call void @use_kernarg_segment_ptr()
   ret void
 }
 
 ; GCN-LABEL: {{^}}use_dispatch_id:
 ; GCN: ; use s[4:5]
 define hidden void @use_dispatch_id() #1 {
define hidden void @use_every_sgpr_input() #1 {
   %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
   %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
   %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
 
   %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
   %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
   %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
 
-  %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
-  %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
-  %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
+  %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
+  %implicitarg.ptr.bc = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %val2 = load volatile i32, i32 addrspace(4)* %implicitarg.ptr.bc
 
   %val3 = call i64 @llvm.amdgcn.dispatch.id()
   call void asm sideeffect "; use $0", "s"(i64 %val3)
 
   %val4 = call i32 @llvm.amdgcn.workgroup.id.x()
   call void asm sideeffect "; use $0", "s"(i32 %val4)
 
   %val5 = call i32 @llvm.amdgcn.workgroup.id.y()
define hidden void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
   %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
   %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
   %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
 
   %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
   %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
   %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
 
-  %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
-  %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
-  %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
+  %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
+  %implicitarg.ptr.bc = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %val2 = load volatile i32, i32 addrspace(4)* %implicitarg.ptr.bc
 
   %val3 = call i64 @llvm.amdgcn.dispatch.id()
   call void asm sideeffect "; use $0", "s"(i64 %val3)
 
   %val4 = call i32 @llvm.amdgcn.workgroup.id.x()
   call void asm sideeffect "; use $0", "s"(i32 %val4)
 
   %val5 = call i32 @llvm.amdgcn.workgroup.id.y()
define hidden void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 {
   %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
   %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
   %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
 
   %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
   %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
   %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
 
-  %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
-  %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
-  %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
+  %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
+  %implicitarg.ptr.bc = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
+  %val2 = load volatile i32, i32 addrspace(4)* %implicitarg.ptr.bc
 
   %val3 = call i64 @llvm.amdgcn.dispatch.id()
   call void asm sideeffect "; use $0", "s"(i64 %val3)
 
   %val4 = call i32 @llvm.amdgcn.workgroup.id.x()
   call void asm sideeffect "; use $0", "s"(i32 %val4)
 
   %val5 = call i32 @llvm.amdgcn.workgroup.id.y()
   call void asm sideeffect "; use $0", "s"(i32 %val5)
 
   %val6 = call i32 @llvm.amdgcn.workgroup.id.z()
   call void asm sideeffect "; use $0", "s"(i32 %val6)
 
   ret void
 }
 
 declare i32 @llvm.amdgcn.workgroup.id.x() #0
 declare i32 @llvm.amdgcn.workgroup.id.y() #0
 declare i32 @llvm.amdgcn.workgroup.id.z() #0
 declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
 declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
+declare noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
 declare i64 @llvm.amdgcn.dispatch.id() #0
 declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
 
 attributes #0 = { nounwind readnone speculatable }
 attributes #1 = { nounwind noinline }

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

 ; GCN-NOT: s[4:5]
 define void @opencl_func_call_implicitarg_ptr_func() #0 {
   call void @func_implicitarg_ptr()
   ret void
 }
 
 ; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr:
 ; GCN: s_waitcnt
-; MESA-DAG: v_mov_b32_e32 v0, s4
-; MESA-DAG: v_mov_b32_e32 v1, s5
-; MESA-DAG: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; MESA: v_mov_b32_e32 v0, s6
-; MESA: v_mov_b32_e32 v1, s7
+; GCN-DAG: v_mov_b32_e32 v0, s4
+; GCN-DAG: v_mov_b32_e32 v1, s5
+; GCN-DAG: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0
+; GCN-DAG: s_load_dword s{{[0-9]+}}, [[NULL]], 0x0
+
 ; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
 
-; HSA: v_mov_b32_e32 v0, s4
-; HSA: v_mov_b32_e32 v1, s5
-; HSA: flat_load_dword v0, v[0:1]
-; HSA: v_mov_b32_e32 v0, s6
-; HSA: v_mov_b32_e32 v1, s7
 ; HSA: flat_load_dword v0, v[0:1]
 
 ; GCN: s_waitcnt vmcnt(0)
 define void @func_kernarg_implicitarg_ptr() #0 {
   %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
   %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
   %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
   ret void
 }
 
 ; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
 ; GCN: s_waitcnt
-; MESA-DAG: v_mov_b32_e32 v0, s4
-; MESA-DAG: v_mov_b32_e32 v1, s5
-; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; MESA-DAG: v_mov_b32_e32 v0, s6
-; MESA-DAG: v_mov_b32_e32 v1, s7
-; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-
+; GCN-DAG: v_mov_b32_e32 v0, s4
+; GCN-DAG: v_mov_b32_e32 v1, s5
+; GCN-DAG: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0
+; GCN-DAG: s_load_dword s{{[0-9]+}}, [[NULL]], 0x0
 
-; HSA: v_mov_b32_e32 v0, s4
-; HSA: v_mov_b32_e32 v1, s5
-; HSA: flat_load_dword v0, v[0:1]
-
-; HSA: v_mov_b32_e32 v0, s6
-; HSA: v_mov_b32_e32 v1, s7
+; MESA: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
 ; HSA: flat_load_dword v0, v[0:1]
 
 ; GCN: s_waitcnt vmcnt(0)
 define void @opencl_func_kernarg_implicitarg_ptr() #0 {
   %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
   %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
   %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
   %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
   %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
   %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
   ret void
 }
 
 ; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func:
-; GCN: s_add_u32 s6, s4, 0x70
-; GCN: s_addc_u32 s7, s5, 0
+; GCN: s_add_u32 s4, s4, 0x70
+; GCN: s_addc_u32 s5, s5, 0
 ; GCN: s_swappc_b64
 define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 {
   call void @func_kernarg_implicitarg_ptr()
   ret void
 }
 
 ; GCN-LABEL: {{^}}kernel_implicitarg_no_struct_align_padding:
 ; HSA: kernarg_segment_byte_size = 120