This is an archive of the discontinued LLVM Phabricator instance.

Differential D76076

[HIP] Mark kernels with uniform-work-group-size=true
ClosedPublic

Authored by yaxunl on Mar 12 2020, 9:51 AM.

Details

Reviewers
b-sumner
rampitec
Commits
rG0ffb12ca67fd: [HIP] Mark kernels with uniform-work-group-size=true

Diff Detail

Event Timeline

yaxunl created this revision.Mar 12 2020, 9:51 AM
Herald added subscribers: kerbowa, nhaehnle, jvesely. · View Herald TranscriptMar 12 2020, 9:51 AM
yaxunl added a reviewer: rampitec.Mar 12 2020, 12:53 PM
rampitec accepted this revision.Mar 12 2020, 1:20 PM

LGTM

This revision is now accepted and ready to land.Mar 12 2020, 1:20 PM
Closed by commit rG0ffb12ca67fd: [HIP] Mark kernels with uniform-work-group-size=true (authored by yaxunl). · Explain WhyMar 13 2020, 4:24 AM
This revision was automatically updated to reflect the committed changes.
Herald added a project: Restricted Project. · View Herald TranscriptMar 13 2020, 4:24 AM

Revision Contents

PathSize
clang/
lib/
CodeGen/
4 lines
test/
CodeGenCUDA/
2 lines

Diff 249962

clang/lib/CodeGen/TargetInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 8,085 Lines • ▼ Show 20 Linesvoid AMDGPUTargetCodeGenInfo::setTargetAttributes(
const bool IsOpenCLKernel = M.getLangOpts().OpenCL && const bool IsOpenCLKernel = M.getLangOpts().OpenCL &&
FD->hasAttr<OpenCLKernelAttr>(); FD->hasAttr<OpenCLKernelAttr>();
const bool IsHIPKernel = M.getLangOpts().HIP && const bool IsHIPKernel = M.getLangOpts().HIP &&
FD->hasAttr<CUDAGlobalAttr>(); FD->hasAttr<CUDAGlobalAttr>();
if ((IsOpenCLKernel || IsHIPKernel) && if ((IsOpenCLKernel || IsHIPKernel) &&
(M.getTriple().getOS() == llvm::Triple::AMDHSA)) (M.getTriple().getOS() == llvm::Triple::AMDHSA))
F->addFnAttr("amdgpu-implicitarg-num-bytes", "56"); F->addFnAttr("amdgpu-implicitarg-num-bytes", "56");
if (IsHIPKernel)
F->addFnAttr("uniform-work-group-size", "true");
const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>(); const auto *FlatWGS = FD->getAttr<AMDGPUFlatWorkGroupSizeAttr>();
if (ReqdWGS || FlatWGS) { if (ReqdWGS || FlatWGS) {
unsigned Min = 0; unsigned Min = 0;
unsigned Max = 0; unsigned Max = 0;
if (FlatWGS) { if (FlatWGS) {
Min = FlatWGS->getMin() Min = FlatWGS->getMin()
->EvaluateKnownConstInt(M.getContext()) ->EvaluateKnownConstInt(M.getContext())
.getExtValue(); .getExtValue();
▲ Show 20 Lines • Show All 2,028 Lines • Show Last 20 Lines

clang/test/CodeGenCUDA/amdgpu-kernel-attrs.cu

Show All 33 Lines
} }
// Make sure this is silently accepted on other targets. // Make sure this is silently accepted on other targets.
// NAMD-NOT: "amdgpu-flat-work-group-size" // NAMD-NOT: "amdgpu-flat-work-group-size"
// NAMD-NOT: "amdgpu-waves-per-eu" // NAMD-NOT: "amdgpu-waves-per-eu"
// NAMD-NOT: "amdgpu-num-vgpr" // NAMD-NOT: "amdgpu-num-vgpr"
// NAMD-NOT: "amdgpu-num-sgpr" // NAMD-NOT: "amdgpu-num-sgpr"
// DEFAULT-DAG: attributes [[FLAT_WORK_GROUP_SIZE_DEFAULT]] = {{.*}}"amdgpu-flat-work-group-size"="1,256" // DEFAULT-DAG: attributes [[FLAT_WORK_GROUP_SIZE_DEFAULT]] = {{.*}}"amdgpu-flat-work-group-size"="1,256"{{.*}}"uniform-work-group-size"="true"
// MAX1024-DAG: attributes [[FLAT_WORK_GROUP_SIZE_DEFAULT]] = {{.*}}"amdgpu-flat-work-group-size"="1,1024" // MAX1024-DAG: attributes [[FLAT_WORK_GROUP_SIZE_DEFAULT]] = {{.*}}"amdgpu-flat-work-group-size"="1,1024"
// CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64]] = {{.*}}"amdgpu-flat-work-group-size"="32,64" // CHECK-DAG: attributes [[FLAT_WORK_GROUP_SIZE_32_64]] = {{.*}}"amdgpu-flat-work-group-size"="32,64"
// CHECK-DAG: attributes [[WAVES_PER_EU_2]] = {{.*}}"amdgpu-waves-per-eu"="2" // CHECK-DAG: attributes [[WAVES_PER_EU_2]] = {{.*}}"amdgpu-waves-per-eu"="2"
// CHECK-DAG: attributes [[NUM_SGPR_32]] = {{.*}}"amdgpu-num-sgpr"="32" // CHECK-DAG: attributes [[NUM_SGPR_32]] = {{.*}}"amdgpu-num-sgpr"="32"
// CHECK-DAG: attributes [[NUM_VGPR_64]] = {{.*}}"amdgpu-num-vgpr"="64" // CHECK-DAG: attributes [[NUM_VGPR_64]] = {{.*}}"amdgpu-num-vgpr"="64"