[compiler-rt][builtins][RISCV] Port __clear_cache to RISC-V Linux

[luismarques]

Summary

Implements __clear_cache for RISC-V Linux.

We can't just use fence.i on Linux, because the Linux thread might be scheduled on another hart, and the fence.i instruction only flushes the icache of the current hart.

Fixes the failures of the compiler-rt tests clear_cache_test.c and enable_execute_stack_test.c for RISC-V.

[asb]

LGTM, thanks!

[luismarques]

Closing revision.
(My commit message clean-up went overboard and accidentally deleted the Differential Revision line).

compiler-rt/lib/builtins/clear_cache.c

#elif defined(__sparc__)
   const size_t len = (uintptr_t)end - (uintptr_t)start;
 
   const uintptr_t mask = ~(dword_size - 1);
   const uintptr_t start_dword = ((uintptr_t)start) & mask;
   const uintptr_t end_dword = ((uintptr_t)start + len + dword_size - 1) & mask;
 
   for (uintptr_t dword = start_dword; dword < end_dword; dword += dword_size)
     __asm__ volatile("flush %0" : : "r"(dword));
+#elif defined(__riscv) && defined(__linux__)
+#define __NR_riscv_flush_icache (244 + 15)
+  register void *start_reg __asm("a0") = start;
+  const register void *end_reg __asm("a1") = end;
+  const register long flags __asm("a2") = 0;
+  const register long syscall_nr __asm("a7") = __NR_riscv_flush_icache;
+  __asm __volatile("ecall"
+                   : "=r"(start_reg)
+                   : "r"(start_reg), "r"(end_reg), "r"(flags), "r"(syscall_nr));
+  assert(start_reg == 0 && "Cache flush syscall failed.");
 #else
 #if __APPLE__
   // On Darwin, sys_icache_invalidate() provides this functionality
   sys_icache_invalidate(start, end - start);
 #else
   compilerrt_abort();
 #endif
 #endif
 }