Extend LaneBitmask to 64 bit

[rampitec]

Summary

This is needed for D74873, AMDGPU going to have 16 bit subregs
and the largest tuple is 32 VGPRs, which results in 64 lanes.

[arsenm]

llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir

43

I would just change the number of 0s here

llvm/include/llvm/MC/LaneBitmask.h

 #include "llvm/Support/Format.h"
 #include "llvm/Support/Printable.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 
   struct LaneBitmask {
     // When changing the underlying type, change the format string as well.
-    using Type = unsigned;
+    using Type = uint64_t;
     enum : unsigned { BitWidth = 8*sizeof(Type) };
-    constexpr static const char *const FormatStr = "%08X";
+    constexpr static const char *const FormatStr = "%016lX";
 
     constexpr LaneBitmask() = default;
     explicit constexpr LaneBitmask(Type V) : Mask(V) {}
 
     constexpr bool operator== (LaneBitmask M) const { return Mask == M.Mask; }
     constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
     constexpr bool operator< (LaneBitmask M)  const { return Mask < M.Mask; }
     constexpr bool none() const { return Mask == 0; }
struct LaneBitmask {
     }
 
     constexpr Type getAsInteger() const { return Mask; }
 
     unsigned getNumLanes() const {
       return countPopulation(Mask);
     }
     unsigned getHighestLane() const {
-      return Log2_32(Mask);
+      return Log2_64(Mask);
     }
 
     static constexpr LaneBitmask getNone() { return LaneBitmask(0); }
     static constexpr LaneBitmask getAll() { return ~LaneBitmask(0); }
     static constexpr LaneBitmask getLane(unsigned Lane) {
       return LaneBitmask(Type(1) << Lane);
     }
 

llvm/lib/CodeGen/MIRParser/MIParser.cpp

if (parseNamedRegister(Reg))
       return true;
     lex();
     LaneBitmask Mask = LaneBitmask::getAll();
     if (consumeIfPresent(MIToken::colon)) {
       // Parse lane mask.
       if (Token.isNot(MIToken::IntegerLiteral) &&
           Token.isNot(MIToken::HexLiteral))
         return error("expected a lane mask");
-      static_assert(sizeof(LaneBitmask::Type) == sizeof(unsigned),
+      static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),
                     "Use correct get-function for lane mask");
       LaneBitmask::Type V;
-      if (getUnsigned(V))
+      if (getUint64(V))
         return error("invalid lane mask value");
       Mask = LaneBitmask(V);
       lex();
     }
     MBB.addLiveIn(Reg, Mask);
   } while (consumeIfPresent(MIToken::comma));
   return false;
 }

llvm/test/CodeGen/AMDGPU/at-least-one-def-value-assert.mir

 # RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -verify-machineinstrs  -run-pass=machine-scheduler -verify-misched -o /dev/null %s  2>&1  | FileCheck %s
 
 # CHECK: *** Bad machine code: No live subrange at use ***
 # CHECK-NEXT: - function:    at_least_one_value_should_be_defined_by_this_mask
 # CHECK-NEXT: - basic block: %bb.0
 # CHECK-NEXT: - instruction: 48B  dead undef %2.sub0:vreg_128 = COPY %0.sub0:vreg_128
 # CHECK-NEXT: - operand 1:   %0.sub0:vreg_128
-# CHECK-NEXT: - interval:    %0 [16r,48r:0)  0@16r L00000002 [16r,32r:0)  0@16r weight:0.000000e+00
+# CHECK-NEXT: - interval:    %0 [16r,48r:0)  0@16r L0000000000000002 [16r,32r:0)  0@16r weight:0.000000e+00
 
 # This used to assert with: !SR.empty() && "At least one value should be defined by this mask"
 
 # This MIR is invalid and should be caught by the verifier. %0.sub0 is
 # used, but not defined. There are also lanes in %0 that are not used
 # or defined anywhere. Previously there was an assertion in the
 # LiveInterval computation, which was more confusing. The invalid
 # LiveRange should be produced and the verifier will catch it.

llvm/test/CodeGen/AMDGPU/postra-machine-sink.mir

 # RUN: llc -march=amdgcn -mcpu=gfx908 -run-pass=postra-machine-sink -verify-machineinstrs -o - %s | FileCheck %s
 
 # Don't sink copy that writes sub-register of another copy source register
 # CHECK-LABEL: name: donotsinkcopy
 # CHECK-LABEL: bb.0:
 # CHECK: renamable $sgpr1 = COPY renamable $sgpr2
 # CHECK-LABEL: bb.1:
-# CHECK: liveins: $sgpr0_sgpr1:0x00000003
+# CHECK: liveins: $sgpr0_sgpr1:0x0000000000000003
 # CHECK: renamable $vgpr1_vgpr2 = COPY renamable $sgpr0_sgpr1
 
 ---
 name: donotsinkcopy
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $sgpr0, $sgpr2, $vgpr3

llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir

 ###############################################################################
 # We are expecting four "Bad machine code" when subregister liveness is used.
 #
 # CHECK-SUB-NOT: Bad machine code
 #
 # CHECK-SUB: Bad machine code: Live range continues after dead def flag
 # CHECK_SUB-NEXT: function:    test_fail
 # CHECK-SUB:      v. register: %0
-# CHECK-SUB:      lanemask:    00000002
+# CHECK-SUB:      lanemask:    {{0*}}2
 #
 # CHECK-SUB-NOT: Bad machine code
 #
 # CHECK-SUB: Bad machine code: Live range continues after dead def flag
 # CHECK-SUB-NEXT: function:    test_fail
 # CHECK-SUB:      v. register: %1
-# CHECK-SUB:      lanemask:    00000002
+# CHECK-SUB:      lanemask:    {{0*}}2
 #
 # CHECK-SUB-NOT: Bad machine code
 #
 # CHECK-SUB: Bad machine code: Live range continues after dead def flag
 # CHECK-SUB-NEXT: function:    test_fail
 # CHECK-SUB:      v. register: %1
-# CHECK-SUB:      lanemask:    00000001
+# CHECK-SUB:      lanemask:    {{0*}}1
 #
 # CHECK-SUB: Bad machine code: Live range continues after dead def flag
 # CHECK-SUB-NEXT: function:    test_fail
 # CHECK:          v. register: %2
 #
 # CHECK-SUB-NOT: Bad machine code
 
 ###############################################################################

llvm/test/CodeGen/MIR/Hexagon/parse-lane-masks.mir

 # RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s
 # Check that the MIR parser can parse lane masks in block liveins.
 
 # CHECK-LABEL: name: foo
 # CHECK: bb.0:
-# CHECK: liveins: $d0:0x00000002, $d1, $d2:0x00000010
+# CHECK: liveins: $d0:0x{{0*}}2, $d1, $d2:0x{{0*}}10
 
 --- |
   define void @foo() {
     ret void
   }
 ...
 
 ---