[XCore] Add instruction pattern for bitrev

[Jim]

Summary

Add support for lowering bitreverse to the bitrev instruction.
Fix https://bugs.llvm.org/show_bug.cgi?id=34628.

[RKSimon]

llvm/lib/Target/XCore/XCoreInstrInfo.td

892

Should you remove int_xcore_bitrev and use bitreverse directly? AFAICT xcore does this in LowerINTRINSIC_WO_CHAIN for crc8?

[Jim]

llvm/lib/Target/XCore/XCoreInstrInfo.td

892

int_xcore_bitrev (intrinsic node from llvm.xcore.bitrev) has to be matched bitrev instruction.
It looks like unable to be removed.

[RKSimon]

OK, in which case lets go with this

llvm/lib/Target/XCore/XCoreISelLowering.cpp

XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
   setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
 
   // Bit Manipulation
   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
   setOperationAction(ISD::ROTL , MVT::i32, Expand);
   setOperationAction(ISD::ROTR , MVT::i32, Expand);
+  setOperationAction(ISD::BITREVERSE , MVT::i32, Legal);
 
   setOperationAction(ISD::TRAP, MVT::Other, Legal);
 
   // Jump tables.
   setOperationAction(ISD::BR_JT, MVT::Other, Custom);
 
   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
   setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);

llvm/lib/Target/XCore/XCoreInstrInfo.td

def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
                   "eet $a, res[$b]", []>;
 
 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
                         "tsetmr r$a, $b", []>;
 
 // Two operand long
 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
                        "bitrev $dst, $src",
                        [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
 
 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
                         "byterev $dst, $src",
                         [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
 
 def CLZ_l2r : _FL2R<0b0000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
                     "clz $dst, $src",
                     [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;

 
 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
           (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
           (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
 def : Pat<(store GRRegs:$val, GRRegs:$addr),
           (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
 
+/// bitrev
+def : Pat<(bitreverse GRRegs:$src), (BITREV_l2r GRRegs:$src)>;
+
 /// cttz
 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
 
 /// trap
 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
 
 ///
 /// branch patterns

llvm/test/CodeGen/XCore/bitrev.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=xcore | FileCheck %s
+
+declare i8 @llvm.bitreverse.i8(i8)
+declare i16 @llvm.bitreverse.i16(i16)
+declare i32 @llvm.bitreverse.i32(i32)
+declare i64 @llvm.bitreverse.i64(i64)
+
+define i8 @bitrev8(i8 %x) nounwind {
+; CHECK-LABEL: bitrev8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r0, r0
+; CHECK-NEXT:    shr r0, r0, 24
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev8.function
+entry:
+  %0 = call i8 @llvm.bitreverse.i8(i8 %x)
+  ret i8 %0
+}
+
+define i16 @bitrev16(i16 %x) nounwind {
+; CHECK-LABEL: bitrev16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r0, r0
+; CHECK-NEXT:    shr r0, r0, 16
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev16.function
+entry:
+  %0 = call i16 @llvm.bitreverse.i16(i16 %x)
+  ret i16 %0
+}
+
+define i32 @bitrev32(i32 %x) nounwind {
+; CHECK-LABEL: bitrev32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r0, r0
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev32.function
+entry:
+  %0 = call i32 @llvm.bitreverse.i32(i32 %x)
+  ret i32 %0
+}
+
+define i64 @bitrev64(i64 %x) nounwind {
+; CHECK-LABEL: bitrev64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bitrev r2, r1
+; CHECK-NEXT:    bitrev r1, r0
+; CHECK-NEXT:    mov r0, r2
+; CHECK-NEXT:    retsp 0
+; CHECK-NEXT:    .cc_bottom bitrev64.function
+entry:
+  %0 = call i64 @llvm.bitreverse.i64(i64 %x)
+  ret i64 %0
+}