[TBLGEN] Allow to override RC weight

[arsenm]

llvm/include/llvm/Target/Target.td

279

Needs more explanation. What does the weight mean?

[rampitec]

llvm/include/llvm/Target/Target.td

279

That's what TargetRegisterClass::getRegClassWeight() will return. It doesn't have much more info though: "Get the weight in units of pressure for this register class."

https://llvm.org/doxygen/classllvm_1_1TargetRegisterInfo.html#a55dc7cf067f4fdc07a902ca0f3e3a87d

Normally tablegen will use weight equal to a number of regunits per register, well "normalized". This value is used to measure register pressure.

[rampitec]

Updated comment.

[arsenm]

llvm/utils/TableGen/RegisterInfoEmitter.cpp

207

Single quotes

[rampitec]

Replaced double with singe quotes in char output.

llvm/include/llvm/Target/Target.td

class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   code AltOrderSelect = [{}];
 
   // Specify allocation priority for register allocators using a greedy
   // heuristic. Classes with higher priority values are assigned first. This is
   // useful as it is sometimes beneficial to assign registers to highly
   // constrained classes first. The value has to be in the range [0,63].
   int AllocationPriority = 0;
 
+  // Weight override for register pressure calculation. This is the value
+  // TargetRegisterClass::getRegClassWeight() will return. The weight is in
+  // units of pressure for this register class. If unset tablegen will
+  // calculate a weight based on a number of register units in this register
+  // class registers. The weight is per register.
+  int Weight = ?;
+
   // The diagnostic type to present when referencing this operand in a match
   // failure error message. If this is empty, the default Match_InvalidOperand
   // diagnostic type will be used. If this is "<name>", a Match_<name> enum
   // value will be generated and used for this operand type. The target
   // assembly parser is responsible for converting this into a user-facing
   // diagnostic message.
   string DiagnosticType = "";
 

llvm/lib/Target/AMDGPU/R600RegisterInfo.h

 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
 
 #define GET_REGINFO_HEADER
 #include "R600GenRegisterInfo.inc"
 
 namespace llvm {
 
 struct R600RegisterInfo final : public R600GenRegisterInfo {
-  RegClassWeight RCW;
-
-  R600RegisterInfo();
+  R600RegisterInfo() : R600GenRegisterInfo(0) {}
 
   /// \returns the sub reg enum value for the given \p Channel
   /// (e.g. getSubRegFromChannel(0) -> R600::sub0)
   static unsigned getSubRegFromChannel(unsigned Channel);
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   Register getFrameRegister(const MachineFunction &MF) const override;
 
   /// get the HW encoding for a register's channel.
   unsigned getHWRegChan(unsigned reg) const;
 
   unsigned getHWRegIndex(unsigned Reg) const;
 
   /// get the register class of the specified type to use in the
   /// CFGStructurizer
   const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
 
-  const RegClassWeight &
-    getRegClassWeight(const TargetRegisterClass *RC) const override;
-
   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
     return false;
   }
 
   // \returns true if \p Reg can be defined in one ALU clause and used in
   // another.
   bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
 

llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp

 #include "AMDGPUTargetMachine.h"
 #include "R600Defines.h"
 #include "R600InstrInfo.h"
 #include "R600MachineFunctionInfo.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 
 using namespace llvm;
 
-R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
-  RCW.RegWeight = 0;
-  RCW.WeightLimit = 0;
-}
-
 #define GET_REGINFO_TARGET_DESC
 #include "R600GenRegisterInfo.inc"
 
 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) {
   static const uint16_t SubRegFromChannelTable[] = {
     R600::sub0, R600::sub1, R600::sub2, R600::sub3,
     R600::sub4, R600::sub5, R600::sub6, R600::sub7,
     R600::sub8, R600::sub9, R600::sub10, R600::sub11,

 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
                                                                    MVT VT) const {
   switch(VT.SimpleTy) {
   default:
   case MVT::i32: return &R600::R600_TReg32RegClass;
   }
 }
 
-const RegClassWeight &R600RegisterInfo::getRegClassWeight(
-  const TargetRegisterClass *RC) const {
-  return RCW;
-}
-
 bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
   assert(!Register::isVirtualRegister(Reg));
 
   switch (Reg) {
   case R600::OQAP:
   case R600::OQBP:
   case R600::AR_X:
     return false;

llvm/lib/Target/AMDGPU/R600RegisterInfo.td

 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 def AR_X : R600Reg<"AR.x", 0>;
 def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;
 
 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
-                          (add (sequence "ArrayBase%u", 448, 480))>;
+                          (add (sequence "ArrayBase%u", 448, 480))> {
+  let Weight = 0;
+}
 // special registers for ALU src operands
 // const buffer reference, SRCx_SEL contains index
 def ALU_CONST : R600Reg<"CBuf", 0>;
 // interpolation param reference, SRCx_SEL contains index
 def ALU_PARAM : R600Reg<"Param", 0>;
 
+let Weight = 0 in {
 let isAllocatable = 0 in {
 
 def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
 
 // We only use Addr_[YZW] for vertical vectors.
 // FIXME if we add more vertical vector registers we will need to ad more
 // registers to these classes.
 def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;

 >;
 
 def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32, i64, f64], 64,
                                 (add (sequence "T%u_XY", 0, 63))>;
 
 def R600_Reg64Vertical : RegisterClass<"AMDGPU", [v2f32, v2i32], 64,
                                       (add V01_X, V01_Y, V01_Z, V01_W,
                                            V23_X, V23_Y, V23_Z, V23_W)>;
+} // End let Weight = 0

llvm/test/TableGen/rc-weight-override.td

+// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
+
+include "reg-with-subregs-common.td"
+
+// CHECK-LABEL: static const RegClassWeight RCWeightTable[] = {
+// CHECK: {1, 256}, // GPR32
+// CHECK: {2, 256}, // GPR_64
+
+// CHECK: {0, 256}, // GPR_64_W0
+def GPR_64_W0 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
+  let Weight = 0;
+}
+
+// CHECK: {1, 256}, // GPR_64_W1
+def GPR_64_W1 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
+  let Weight = 1;
+}
+
+// CHECK: {8, 256}, // GPR_64_W8
+def GPR_64_W8 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
+  let Weight = 8;
+}
+
+// CHECK: {32, 256}, // GPR_1024

llvm/utils/TableGen/CodeGenRegisters.h

public:
 
     // Get the set of registers.  This set contains the same registers as
     // getOrder(0).
     const CodeGenRegister::Vec &getMembers() const { return Members; }
 
     // Get a bit vector of TopoSigs present in this register class.
     const BitVector &getTopoSigs() const { return TopoSigs; }
 
+    // Get a weight of this register class.
+    unsigned getWeight(const CodeGenRegBank&) const;
+
     // Populate a unique sorted list of units from a register set.
     void buildRegUnitSet(const CodeGenRegBank &RegBank,
                          std::vector<unsigned> &RegUnits) const;
 
     CodeGenRegisterClass(CodeGenRegBank&, Record *R);
     CodeGenRegisterClass(CodeGenRegisterClass&) = delete;
 
     // A key representing the parts of a register class used for forming

llvm/utils/TableGen/CodeGenRegisters.cpp

for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
         Orders[i].push_back(Super.Orders[i][j]);
 }
 
 bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
   return std::binary_search(Members.begin(), Members.end(), Reg,
                             deref<std::less<>>());
 }
 
+unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank& RegBank) const {
+  if (TheDef && !TheDef->isValueUnset("Weight"))
+    return TheDef->getValueAsInt("Weight");
+
+  if (Members.empty() || Artificial)
+    return 0;
+
+  return (*Members.begin())->getWeight(RegBank);
+}
+
 namespace llvm {
 
   raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
     OS << "{ " << K.RSI;
     for (const auto R : *K.Members)
       OS << ", " << R->getName();
     return OS << " }";
   }

llvm/utils/TableGen/RegisterInfoEmitter.cpp

EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
   unsigned NumSets = RegBank.getNumRegPressureSets();
 
   OS << "/// Get the weight in units of pressure for this register class.\n"
      << "const RegClassWeight &" << ClassName << "::\n"
      << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
      << "  static const RegClassWeight RCWeightTable[] = {\n";
   for (const auto &RC : RegBank.getRegClasses()) {
     const CodeGenRegister::Vec &Regs = RC.getMembers();
+    OS << "    {" << RC.getWeight(RegBank) << ", ";
     if (Regs.empty() || RC.Artificial)
-      OS << "    {0, 0";
+      OS << '0';
     else {
       std::vector<unsigned> RegUnits;
       RC.buildRegUnitSet(RegBank, RegUnits);
-      OS << "    {" << (*Regs.begin())->getWeight(RegBank)
-         << ", " << RegBank.getRegUnitSetWeight(RegUnits);
+      OS << RegBank.getRegUnitSetWeight(RegUnits);
     }
     OS << "},  \t// " << RC.getName() << "\n";
   }
   OS << "  };\n"
      << "  return RCWeightTable[RC->getID()];\n"
      << "}\n\n";
 
   // Reasonable targets (not ARMv7) have unit weight for all units, so don't