[SystemZ] Support the kernel backchain

[jonpa]

Summary

In order to build the Linux kernel, the back chain must be supported together with packed-stack. The back chain is then stored topmost in the register save area.

[jonpa]

allow packed-stack in most of the cases where it's currently forbidden (with varargs, if the frame address is taken, and with backchain) -- since packed-stack is then not just an optimization, but an ABI change

Packed-stack stack is now also allowed with the back chain and with the frame address taken. I am however unsure of what to do with the varargs since this is hard coded all the way from the front end. It seems that GCC is keeping the standard offsets into the reg-save area. What would varargs with packed-stack in llvm mean?

lowerFRAMEADDR(): According to the documentation, zero can be returned if it cannot be identified, which this patch does when the back chain is not present. GCC seems to return just the address of where it would have been even if it is not present (then containing the saved %r15 reg instead). Doing it this way simplifies lowerFRAMEADDR(), I would think.

[jonpa]

Allow packed-stack with varargs, placing the vararg arguments on the default slots in the reg save area.

Maybe move the checks in usePackedStack() to SystemZDAGToDAGISel::runOnMachineFunction()?

[jonpa]

It seems that compiling a vararg function with gcc -mpacked-stack and -msoft-float places the stored GPRs in the default slots. However, by adding also -backchain (in addition to the previous two args) the GPRs are saved right below the backchain, which is at offset 152 (topmost). This patch does currently not move up the GPRs in the case of saving the backchain, but. I am guessing it should (in order to have "constant and known distance from the backchain to the return address")? If so, I suppose the the front-end should emit a different offset for vararg reg arguments in case of packed-stack + soft-float. Could it be the same regardless of backchain, or?

[uweigand]

In D74506#1877948, @jonpa wrote:

It seems that compiling a vararg function with gcc -mpacked-stack and -msoft-float places the stored GPRs in the default slots.

Looks like it does, but this isn't really required. You might as well store the GPRs right at the top of the save area.

However, by adding also -backchain (in addition to the previous two args) the GPRs are saved right below the backchain, which is at offset 152 (topmost). This patch does currently not move up the GPRs in the case of saving the backchain, but. I am guessing it should (in order to have "constant and known distance from the backchain to the return address")?

Yes, this is definitely required. Otherwise backtracking using the kernel backchain will not work.

If so, I suppose the the front-end should emit a different offset for vararg reg arguments in case of packed-stack + soft-float. Could it be the same regardless of backchain, or?

No, the offsets must remain the same, or else the ABI of the va_list type will change. (It must be possible to create a va_list in a function that is built with -mpacked-stack, and pass that list to another function built with -mno-packed-stack to use va_arg on that va_list.)

Instead, you should store the GPRs whereever they need to be stored (at or near the top of the save area), and the compute from that the appropriate value to be stored into the reg_save_area slot in the va_list struct. So for example, if you store r15 right at the top of the save area (sp + 152), then you should set reg_save_area to sp + 32; if you store r15 right below the back chain (sp + 144), then you should set reg_save_area to sp + 24 etc. That way, all existing va_arg code accessing this va_list will find the saved GPRs at the right position. (It won't find saved FPRs -- but it won't look for those if it is built with -msoft-float, and -msoft-float *is* an ABI changing option, so it's OK to require everything to be built with the same setting here.)

To implement this, you'll need to change the place in SystemZTargetLowering::LowerFormalArguments where the value to be used for reg_save_area is set:

int64_t RegSaveOffset = -SystemZMC::CallFrameSize;
unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
FuncInfo->setRegSaveFrameIndex(RegSaveIndex);

This should take into account instead the specific offset where you've decided to save GPRs to.

[jonpa]

Thank you for review. Patch updated accordingly.

Also, I refactored assignCalleeSavedSpillSlots() to not duplicate code in the case of packed-stack. That refactoring alone is this file:

refac_assignCSSSlots.patch4 KBDownload

[uweigand]

Yes, this now looks correct to me. However, we now have duplicated computation between LowerFormalArguments and assignCalleeSavedSpillSlots again, which I don't really like.

I'm wondering whether the best solution wouldn't be to simply make the SystemZFrameLowering::getRegSpillOffset routine take packed stack into account itself. E.g. something like this:

unsigned getRegSpillOffset(const MachineFunction &MF, unsigned Reg) const {
    unsigned Offset = RegSpillOffsets[Reg];
    if (usePackedStack(MF)) {
      if (SystemZ::GR64BitRegClass.contains(Reg)) {
        if (!(IsVarArg && !SoftFloat)) {
	​    // Put all GPRs at the top of the Register save area with packed
	​    // stack. Make room for the backchain if needed.
	​    Offset += BackChain ? 24 : 32;
        } else
  ​        Offset = 0;
    }
    return Offset;
}

and then use that function throughout LowerFormalArguments and assignCalleeSavedSpillSlots ...

clang/lib/Driver/ToolChains/Clang.cpp

2017

It's a bit weird to hard-code only "-mhard-float" here. I guess this is because we may not actually have any "getLastArg" since hard-float is the default? In that case I guess we might as well hard-code the whole string.

llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

486

SystemZMC::CallFrameSize - 8 would be nicer than the hard-coded 152.

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1469

See main comment about this duplicated logic here.

3257

Hmm, GCC will always return the address where the back-chain would have been, even if it isn't emitted. Not sure whether that is very useful, but maybe we should emulate it simply for compatibility reasons ...

[jonpa]

However, we now have duplicated computation between LowerFormalArguments and assignCalleeSavedSpillSlots again, which I don't really like.

I'm wondering whether the best solution wouldn't be to simply make the SystemZFrameLowering::getRegSpillOffset routine take packed stack into account itself.

Yes, that seems even better :-) getRegSpillOffset() MF argument non-const due to usePackedStack().

clang/lib/Driver/ToolChains/Clang.cpp

2017

yes

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

3257

I thought it might be bad to create two stack slots to the same location (slot of abscent backchain / R15), but it appears to be fine.

However, if creating that slot in case of no saved regs but with a local area, as in frameaddr-02.ll:fp1f, this ends up actually creating extra stack space for the backchain without using it.

Not sure what would be best to do in that case if not returning 0...

[uweigand]

OK, just a few more small comments, otherwise looks really good now. Thanks!

llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

124

Maybe easier to understand:

int CurrOffset = -SystemZMC::CallFrameSize;
if (usePackedStack(MF))
  CurrOffset += StartSPOffset;

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1478

I believe this now needs to be -SystemZMC::CallFrameSize + Offset instead of RegSaveOffset + Offset.

3254

We probably shoud use usePackedStack here for consistency.

3257

I see. I guess it's fine to return 0 in that case then. (This is anyway not a mode that's used by real-world use cases.)

[jonpa]

Thanks for review - patch updated.

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1478

I think that should be equivalent due to the '!(IsVarArg && !SoftFloat)' check in getRegSpillOffset().

Would it be clearer to use -SystemZMC::CallFrameSize here still?

[uweigand]

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

1478

Yes, since if there were any offset, it would now be included in getRegSpillOffset ... Right now, it seems like it would be added twice (since you're adding the output of two getRegSpillOffset calls).

[jonpa]

Patch updated per review to use -SystemZMC::CallFrameSize in LowerFormalArguments().

[uweigand]

LGTM, thanks!

clang/lib/Driver/ToolChains/Clang.cpp

 }
 
 void Clang::AddSystemZTargetArgs(const ArgList &Args,
                                  ArgStringList &CmdArgs) const {
   bool HasBackchain = Args.hasFlag(options::OPT_mbackchain,
                                    options::OPT_mno_backchain, false);
   bool HasPackedStack = Args.hasFlag(options::OPT_mpacked_stack,
                                      options::OPT_mno_packed_stack, false);
-  if (HasBackchain && HasPackedStack) {
+  systemz::FloatABI FloatABI =
+      systemz::getSystemZFloatABI(getToolChain().getDriver(), Args);
+  bool HasSoftFloat = (FloatABI == systemz::FloatABI::Soft);
+  if (HasBackchain && HasPackedStack && !HasSoftFloat) {
     const Driver &D = getToolChain().getDriver();
     D.Diag(diag::err_drv_unsupported_opt)
-      << Args.getLastArg(options::OPT_mpacked_stack)->getAsString(Args) +
-      " " + Args.getLastArg(options::OPT_mbackchain)->getAsString(Args);
+      << "-mpacked-stack -mbackchain -mhard-float";
   }
   if (HasBackchain)
     CmdArgs.push_back("-mbackchain");
   if (HasPackedStack)
     CmdArgs.push_back("-mpacked-stack");
-
-  systemz::FloatABI FloatABI =
-      systemz::getSystemZFloatABI(getToolChain().getDriver(), Args);
-
-  if (FloatABI == systemz::FloatABI::Soft) {
+  if (HasSoftFloat) {
     // Floating point operations and argument passing are soft.
     CmdArgs.push_back("-msoft-float");
     CmdArgs.push_back("-mfloat-abi");
     CmdArgs.push_back("soft");
   }
 }
 
 static void addX86AlignBranchArgs(const Driver &D, const ArgList &Args,

clang/test/Driver/mbackchain.c

 // RUN: %clang -target s390x -c -### %s -mpacked-stack -mbackchain 2>&1 | FileCheck %s
+// RUN: %clang -target s390x -c -### %s -mpacked-stack -mbackchain -msoft-float \
+// RUN:   2>&1 | FileCheck %s --check-prefix=KERNEL-BUILD
 
-// CHECK: error: unsupported option '-mpacked-stack -mbackchain'
+// CHECK: error: unsupported option '-mpacked-stack -mbackchain -mhard-float'
+// KERNEL-BUILD-NOT: error: unsupported option

llvm/lib/Target/SystemZ/SystemZFrameLowering.h

public:
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
   int getFrameIndexReference(const MachineFunction &MF, int FI,
                              unsigned &FrameReg) const override;
   MachineBasicBlock::iterator
   eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MI) const override;
 
   // Return the byte offset from the incoming stack pointer of Reg's
-  // ABI-defined save slot.  Return 0 if no slot is defined for Reg.
-  unsigned getRegSpillOffset(unsigned Reg) const {
-    return RegSpillOffsets[Reg];
-  }
+  // ABI-defined save slot.  Return 0 if no slot is defined for Reg.  Adjust
+  // the offset in case MF has packed-stack.
+  unsigned getRegSpillOffset(MachineFunction &MF, unsigned Reg) const;
 
   // Get or create the frame index of where the old frame pointer is stored.
   int getOrCreateFramePointerSaveIndex(MachineFunction &MF) const;
 };
 } // end namespace llvm
 
 #endif

llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

SystemZFrameLowering::SystemZFrameLowering()
   // These offsets are relative to the start of the register save area.
   RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
   for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
     RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
 }
 
 static bool usePackedStack(MachineFunction &MF) {
   bool HasPackedStackAttr = MF.getFunction().hasFnAttribute("packed-stack");
-  bool IsVarArg = MF.getFunction().isVarArg();
-  bool CallConv = MF.getFunction().getCallingConv() != CallingConv::GHC;
   bool BackChain = MF.getFunction().hasFnAttribute("backchain");
-  bool FramAddressTaken = MF.getFrameInfo().isFrameAddressTaken();
-  if (HasPackedStackAttr && BackChain)
-    report_fatal_error("packed-stack with backchain is currently unsupported.");
-  return HasPackedStackAttr && !IsVarArg && CallConv && !BackChain &&
-         !FramAddressTaken;
+  bool SoftFloat = MF.getSubtarget<SystemZSubtarget>().hasSoftFloat();
+  if (HasPackedStackAttr && BackChain && !SoftFloat)
+    report_fatal_error("packed-stack + backchain + hard-float is unsupported.");
+  bool CallConv = MF.getFunction().getCallingConv() != CallingConv::GHC;
+  return HasPackedStackAttr && CallConv;
 }
 
 bool SystemZFrameLowering::
 assignCalleeSavedSpillSlots(MachineFunction &MF,
                             const TargetRegisterInfo *TRI,
                             std::vector<CalleeSavedInfo> &CSI) const {
   SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
   MachineFrameInfo &MFFrame = MF.getFrameInfo();
   bool IsVarArg = MF.getFunction().isVarArg();
   if (CSI.empty())
     return true; // Early exit if no callee saved registers are modified!
 
   unsigned LowGPR = 0;
   unsigned HighGPR = SystemZ::R15D;
   int StartSPOffset = SystemZMC::CallFrameSize;
-  int CurrOffset;
-  if (!usePackedStack(MF)) {
-    for (auto &CS : CSI) {
-      unsigned Reg = CS.getReg();
-      int Offset = RegSpillOffsets[Reg];
-      if (Offset) {
-        if (SystemZ::GR64BitRegClass.contains(Reg) && StartSPOffset > Offset) {
-          LowGPR = Reg;
-          StartSPOffset = Offset;
-        }
-        Offset -= SystemZMC::CallFrameSize;
-        int FrameIdx = MFFrame.CreateFixedSpillStackObject(8, Offset);
-        CS.setFrameIdx(FrameIdx);
-      } else
-        CS.setFrameIdx(INT32_MAX);
-    }
+    int Offset = getRegSpillOffset(MF, Reg);
 
-    // Save the range of call-saved registers, for use by the
-    // prologue/epilogue inserters.
-    ZFI->setRestoreGPRRegs(LowGPR, HighGPR, StartSPOffset);
-    if (IsVarArg) {
-      // Also save the GPR varargs, if any.  R6D is call-saved, so would
-      // already be included, but we also need to handle the call-clobbered
-      // argument registers.
-      unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
-      if (FirstGPR < SystemZ::NumArgGPRs) {
-        unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
-        int Offset = RegSpillOffsets[Reg];
-        if (StartSPOffset > Offset) {
-          LowGPR = Reg; StartSPOffset = Offset;
-        }
-      }
-    }
-    ZFI->setSpillGPRRegs(LowGPR, HighGPR, StartSPOffset);
+      int Offset = getRegSpillOffset(MF, Reg);
 
-    CurrOffset = -SystemZMC::CallFrameSize;
-  } else {
-    // Packed stack: put all the GPRs at the top of the Register save area.
-    uint32_t LowGR64Num = UINT32_MAX;
-    for (auto &CS : CSI) {
-      unsigned Reg = CS.getReg();
-      if (SystemZ::GR64BitRegClass.contains(Reg)) {
-        unsigned GR64Num = SystemZMC::getFirstReg(Reg);
-        int Offset = -8 * (15 - GR64Num + 1);
-        if (LowGR64Num > GR64Num) {
-          LowGR64Num = GR64Num;
-          StartSPOffset = SystemZMC::CallFrameSize + Offset;
-        }
-        int FrameIdx = MFFrame.CreateFixedSpillStackObject(8, Offset);
-        CS.setFrameIdx(FrameIdx);
-      } else
-        CS.setFrameIdx(INT32_MAX);
-    }
-    if (LowGR64Num < UINT32_MAX)
-      LowGPR = SystemZMC::GR64Regs[LowGR64Num];
-
-    // Save the range of call-saved registers, for use by the
-    // prologue/epilogue inserters.
-    ZFI->setRestoreGPRRegs(LowGPR, HighGPR, StartSPOffset);
-    ZFI->setSpillGPRRegs(LowGPR, HighGPR, StartSPOffset);
-
-    CurrOffset = LowGPR ? -(SystemZMC::CallFrameSize - StartSPOffset) : 0;
-  }
-
   // Create fixed stack objects for the remaining registers.
+  int CurrOffset = !usePackedStack(MF)
+                       ? -SystemZMC::CallFrameSize
+                       : -(SystemZMC::CallFrameSize - StartSPOffset);
   for (auto &CS : CSI) {
     if (CS.getFrameIdx() != INT32_MAX)
       continue;
     unsigned Reg = CS.getReg();
     const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
     unsigned Size = TRI->getSpillSize(*RC);
     CurrOffset -= Size;
     assert(CurrOffset % 8 == 0 &&
if (StackSize) {
 
     // Add CFI for the allocation.
     unsigned CFIIndex = MF.addFrameInst(
         MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
     BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
         .addCFIIndex(CFIIndex);
     SPOffsetFromCFA += Delta;
 
-    if (StoreBackchain)
+    if (StoreBackchain) {
+      // The back chain is stored topmost with packed-stack.
+      int Offset = usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0;
       BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
-        .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0)
-        .addReg(0);
+        .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D)
+        .addImm(Offset).addReg(0);
+    }
   }
 
   if (HasFP) {
     // Copy the base of the frame to R11.
     BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
       .addReg(SystemZ::R15D);
 
     // Add CFI for the new frame location.
case SystemZ::ADJCALLSTACKUP:
     return MBB.erase(MI);
     break;
 
   default:
     llvm_unreachable("Unexpected call frame instruction");
   }
 }
 
+unsigned SystemZFrameLowering::getRegSpillOffset(MachineFunction &MF,
+                                                 unsigned Reg) const {
+  bool IsVarArg = MF.getFunction().isVarArg();
+  bool BackChain = MF.getFunction().hasFnAttribute("backchain");
+  bool SoftFloat = MF.getSubtarget<SystemZSubtarget>().hasSoftFloat();
+  unsigned Offset = RegSpillOffsets[Reg];
+  if (usePackedStack(MF) && !(IsVarArg && !SoftFloat)) {
+    if (SystemZ::GR64BitRegClass.contains(Reg))
+      // Put all GPRs at the top of the Register save area with packed
+      // stack. Make room for the backchain if needed.
+      Offset += BackChain ? 24 : 32;
+    else
+      Offset = 0;
+  }
+  return Offset;
+}
+
 int SystemZFrameLowering::
 getOrCreateFramePointerSaveIndex(MachineFunction &MF) const {
   SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
   int FI = ZFI->getFramePointerSaveIndex();
   if (!FI) {
     MachineFrameInfo &MFFrame = MF.getFrameInfo();
-    FI = MFFrame.CreateFixedObject(8, -SystemZMC::CallFrameSize, false);
+    // The back chain is stored topmost with packed-stack.
+    int Offset = usePackedStack(MF) ? -8 : -SystemZMC::CallFrameSize;
+    FI = MFFrame.CreateFixedObject(8, Offset, false);
     ZFI->setFramePointerSaveIndex(FI);
   }
   return FI;
 }

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

if (IsVarArg) {
 
     // Likewise the address (in the form of a frame index) of where the
     // first stack vararg would be.  The 1-byte size here is arbitrary.
     int64_t StackSize = CCInfo.getNextStackOffset();
     FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, StackSize, true));
 
     // ...and a similar frame index for the caller-allocated save area
     // that will be used to store the incoming registers.
-    int64_t RegSaveOffset = -SystemZMC::CallFrameSize;
+    int64_t RegSaveOffset =
+      -SystemZMC::CallFrameSize + TFL->getRegSpillOffset(MF, SystemZ::R2D) - 16;
     unsigned RegSaveIndex = MFI.CreateFixedObject(1, RegSaveOffset, true);
     FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
 
     // Store the FPR varargs in the reserved frame slots.  (We store the
     // GPRs as part of the prologue.)
     if (NumFixedFPRs < SystemZ::NumArgFPRs && !useSoftFloat()) {
       SDValue MemOps[SystemZ::NumArgFPRs];
       for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
-        unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
+        unsigned Offset = TFL->getRegSpillOffset(MF, SystemZ::ArgFPRs[I]);
         int FI = MFI.CreateFixedObject(8, RegSaveOffset + Offset, true);
         SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
         unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
                                      &SystemZ::FP64BitRegClass);
         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
         MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
                                  MachinePointerInfo::getFixedStack(MF, FI));
       }
       // Join the stores, which are independent of one another.
SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   MFI.setFrameAddressIsTaken(true);
 
   SDLoc DL(Op);
   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
 
+  // Return null if the back chain is not present.
+  bool HasPackedStackAttr = MF.getFunction().hasFnAttribute("packed-stack");
+  bool HasBackChain = MF.getFunction().hasFnAttribute("backchain");
+  if (HasPackedStackAttr && !HasBackChain)
+    return DAG.getConstant(0, DL, PtrVT);
+
   // By definition, the frame address is the address of the back chain.
   auto *TFL =
       static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
   int BackChainIdx = TFL->getOrCreateFramePointerSaveIndex(MF);
   SDValue BackChain = DAG.getFrameIndex(BackChainIdx, PtrVT);
 
   // FIXME The frontend should detect this case.
   if (Depth > 0) {

llvm/test/CodeGen/SystemZ/frame-23.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+;
+; Test backchain with packed-stack, which requires soft-float.
+
+attributes #0 = { nounwind "backchain" "packed-stack" "use-soft-float"="true" }
+define i64 @fun0(i64 %a) #0 {
+; CHECK-LABEL: fun0:
+; CHECK:      stmg  %r14, %r15, 136(%r15)
+; CHECK-NEXT: lgr %r1, %r15
+; CHECK-NEXT: aghi  %r15, -24
+; CHECK-NEXT: stg %r1, 152(%r15)
+; CHECK-NEXT: brasl %r14, foo@PLT
+; CHECK-NEXT: lmg %r14, %r15, 160(%r15)
+; CHECK-NEXT: br  %r14
+entry:
+  %call = call i64 @foo(i64 %a)
+  ret i64 %call
+}
+
+declare i64 @foo(i64)

llvm/test/CodeGen/SystemZ/frame-24.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+;
+; Test saving of vararg registers and backchain with packed stack.
+
+%struct.__va_list_tag = type { i64, i64, i8*, i8* }
+declare void @llvm.va_start(i8*)
+
+attributes #0 = { nounwind "packed-stack"="true" }
+define void @fun0(i64 %g0, double %d0, i64 %n, ...) #0 {
+; CHECK-LABEL: fun0:
+; CHECK:      stmg  %r4, %r15, 32(%r15)
+; CHECK-NEXT: aghi  %r15, -192
+; CHECK-NEXT: std %f2, 328(%r15)
+; CHECK-NEXT: std %f4, 336(%r15)
+; CHECK-NEXT: std %f6, 344(%r15)
+; CHECK-NEXT: la  %r0, 352(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: la  %r0, 192(%r15)
+; CHECK-NEXT: stg %r0, 184(%r15)
+; CHECK-NEXT: mvghi 160(%r15), 2
+; CHECK-NEXT: mvghi 168(%r15), 1
+; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
+; CHECK-NEXT: br  %r14
+entry:
+  %vl = alloca [1 x %struct.__va_list_tag], align 8
+  %0 = bitcast [1 x %struct.__va_list_tag]* %vl to i8*
+  call void @llvm.va_start(i8* nonnull %0)
+  ret void
+}
+
+attributes #1 = { nounwind "packed-stack"="true" "use-soft-float"="true" }
+define void @fun1(i64 %g0, double %d0, i64 %n, ...) #1 {
+; CHECK-LABEL: fun1:
+; CHECK:      stmg  %r5, %r15, 72(%r15)
+; CHECK-NEXT: aghi  %r15, -160
+; CHECK-NEXT: la  %r0, 192(%r15)
+; CHECK-NEXT: stg %r0, 184(%r15)
+; CHECK-NEXT: la  %r0, 320(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: mvghi 168(%r15), 0
+; CHECK-NEXT: mvghi 160(%r15), 3
+; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
+; CHECK-NEXT: br  %r14
+entry:
+  %vl = alloca [1 x %struct.__va_list_tag], align 8
+  %0 = bitcast [1 x %struct.__va_list_tag]* %vl to i8*
+  call void @llvm.va_start(i8* nonnull %0)
+  ret void
+}
+
+attributes #2 = { nounwind "packed-stack"="true" "use-soft-float"="true" "backchain"}
+define void @fun2(i64 %g0, double %d0, i64 %n, ...) #2 {
+; CHECK-LABEL: fun2:
+; CHECK:      stmg  %r5, %r15, 64(%r15)
+; CHECK-NEXT: lgr %r1, %r15
+; CHECK-NEXT: aghi  %r15, -168
+; CHECK-NEXT: stg %r1, 152(%r15)
+; CHECK-NEXT: la  %r0, 192(%r15)
+; CHECK-NEXT: stg %r0, 184(%r15)
+; CHECK-NEXT: la  %r0, 328(%r15)
+; CHECK-NEXT: stg %r0, 176(%r15)
+; CHECK-NEXT: mvghi 168(%r15), 0
+; CHECK-NEXT: mvghi 160(%r15), 3
+; CHECK-NEXT: lmg %r6, %r15, 240(%r15)
+; CHECK-NEXT: br  %r14
+entry:
+  %vl = alloca [1 x %struct.__va_list_tag], align 8
+  %0 = bitcast [1 x %struct.__va_list_tag]* %vl to i8*
+  call void @llvm.va_start(i8* nonnull %0)
+  ret void
+}
+

llvm/test/CodeGen/SystemZ/frameaddr-02.ll

+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+; Test lowering of @llvm.frameaddress with packed-stack.
+
+; With back chain
+attributes #0 = { nounwind "packed-stack" "backchain" "use-soft-float"="true" }
+define i8* @fp0() #0 {
+entry:
+; CHECK-LABEL: fp0:
+; CHECK:      la   %r2, 152(%r15)
+; CHECK-NEXT: br   %r14
+  %0 = tail call i8* @llvm.frameaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @fp0f() #0 {
+entry:
+; CHECK-LABEL: fp0f:
+; CHECK:      lgr %r1, %r15
+; CHECK-NEXT: aghi  %r15, -16
+; CHECK-NEXT: stg %r1, 152(%r15)
+; CHECK-NEXT: la  %r2, 168(%r15)
+; CHECK-NEXT: aghi  %r15, 16
+; CHECK-NEXT: br  %r14
+  %0 = alloca i64, align 8
+  %1 = tail call i8* @llvm.frameaddress(i32 0)
+  ret i8* %1
+}
+
+; Without back chain
+
+attributes #1 = { nounwind "packed-stack" }
+define i8* @fp1() #1 {
+entry:
+; CHECK-LABEL: fp1:
+; CHECK:      lghi %r2, 0
+; CHECK-NEXT: br   %r14
+  %0 = tail call i8* @llvm.frameaddress(i32 0)
+  ret i8* %0
+}
+
+define i8* @fp1f() #1 {
+entry:
+; CHECK-LABEL: fp1f:
+; CHECK:      aghi  %r15, -8
+; CHECK-NEXT: lghi  %r2, 0
+; CHECK-NEXT: aghi  %r15, 8
+; CHECK-NEXT: br  %r14
+  %0 = alloca i64, align 8
+  %1 = tail call i8* @llvm.frameaddress(i32 0)
+  ret i8* %1
+}
+
+declare i8* @llvm.frameaddress(i32) nounwind readnone