[AArch64] Fix BTI landing pad generation.

[danielkiss]

Summary

In some cases BTI landing pad is inserted even compatible instruction
was there already. Meta instruction does not count in this case
therefore skip them in the check for first instructions in the function.

[ostannard]

llvm/test/CodeGen/AArch64/branch-target-enforcement-metainstruction.ll

1 ↗

(On Diff #244199)

This would be better as a MIR test, so we can be sure there is a meta instruction at the beginning of the function. We already have branch-target-enforcement.mir, which this case could be added to.

[ostannard]

LGTM

[danielkiss]

I don't have commit right, could you please commit it on my behalf?

llvm/lib/Target/AArch64/AArch64BranchTargets.cpp

void AArch64BranchTargets::addBTI(MachineBasicBlock &MBB, bool CouldCall,
   if (CouldCall)
     HintNum |= 2;
   if (CouldJump)
     HintNum |= 4;
   assert(HintNum != 32 && "No target kinds!");
 
   auto MBBI = MBB.begin();
 
+  // Skip the meta instuctions, those will be removed anyway.
+  for (; MBBI != MBB.end() && MBBI->isMetaInstruction(); ++MBBI)
+    ;
+
   // PACI[AB]SP are implicitly BTI JC, so no BTI instruction needed there.
   if (MBBI != MBB.end() && (MBBI->getOpcode() == AArch64::PACIASP ||
                             MBBI->getOpcode() == AArch64::PACIBSP))
     return;
 
   BuildMI(MBB, MBB.begin(), MBB.findDebugLoc(MBB.begin()),
           TII->get(AArch64::HINT))
       .addImm(HintNum);
 }

llvm/test/CodeGen/AArch64/branch-target-enforcement.mir

--- |
 
   .split:                                           ; preds = %lab2, %return
     %merge = phi i8* [ blockaddress(@label_address, %lab2), %return ], [ blockaddress(@label_address, %return), %lab2 ]
     %merge2 = phi i32 [ 1, %return ], [ 2, %lab2 ]
     store i8* %merge, i8** @label_address.addr, align 8
     ret i32 %merge2
   }
 
+  define hidden i32 @debug_ptr_auth() "branch-target-enforcement" {
+  entry:
+    tail call void asm sideeffect "", "~{lr}"()
+    ret i32 0
+  }
+
 ...
 ---
 # External function, could be addres-taken elsewhere so needs BTI JC.
 name:            simple_external
 body:             |
   bb.0.entry:
     ; CHECK-LABEL: name: simple_external
     ; CHECK: HINT 34
bb.2.lab2:
     ; CHECK-NOT: HINT
     liveins: $x8
 
     $x9 = ADRP target-flags(aarch64-page) blockaddress(@label_address, %ir-block.return)
     renamable $w0 = ORRWri $wzr, 1984
     renamable $x9 = ADDXri killed $x9, target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@label_address, %ir-block.return), 0
     STRXui killed renamable $x9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @label_address.addr :: (store 8 into @label_address.addr)
     RET undef $lr, implicit killed $w0
+---
+# When PACIASP is the first real instruction in the functions then BTI should not be inserted.
+name:            debug_ptr_auth
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; CHECK-LABEL: name: debug_ptr_auth
+    ; CHECK-NOT: HINT
+    ; CHECK: DBG_VALUE
+    ; CHECK: frame-setup PACIASP
+    ; CHECK-NOT: HINT
+    ; CHECK: RETAA
+    DBG_VALUE $lr
+    frame-setup PACIASP implicit-def $lr, implicit killed $lr, implicit $sp
+    frame-setup CFI_INSTRUCTION negate_ra_sign_state
+    early-clobber $sp = frame-setup STRXpre killed $lr, $sp, -16 :: (store 8 into %stack.0)
+    INLINEASM &"", 1, 12, implicit-def dead early-clobber $lr
+    $w0 = ORRWrs $wzr, $wzr, 0
+    early-clobber $sp, $lr = frame-destroy LDRXpost $sp, 16 :: (load 8 from %stack.0)
+    RETAA implicit $sp, implicit $lr, implicit killed $w0
 
 ...