This is an archive of the discontinued LLVM Phabricator instance.

[X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models
ClosedPublic

Authored by craig.topper on Feb 10 2020, 1:53 PM.

Details

Summary

Based on uops.info these should have 5 cycle latency as they did on Haswell/Broadwell. I have no additional internal information from Intel.

This was also shown as a discrepancy in the spreadsheet that was sent with an early llvm-dev post about llvm-exegesis.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 10 2020, 1:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 10 2020, 1:53 PM
craig.topper edited the summary of this revision. (Show Details)Feb 10 2020, 1:56 PM
RKSimon accepted this revision.Feb 11 2020, 1:34 AM

LGTM - (Agner agrees as well)

This revision is now accepted and ready to land.Feb 11 2020, 1:34 AM
This revision was automatically updated to reflect the committed changes.