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AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
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Authored by arsenm on Feb 6 2020, 4:48 PM.

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Reviewers

nhaehnle
kerbowa

Summary

When SI_IF is inserted, it constrains the source register with a
register class, which was quite likely a G_ICMP. This was incorrectly
treating it as a scalar, and then applyMappingImpl would end up
producing invalid MIR since this was unexpected.

Also fix not using all VGPR sources for vcc outputs.

Diff Detail

Event Timeline

arsenm created this revision.Feb 6 2020, 4:48 PM

Herald added a project: Restricted Project. · View Herald TranscriptFeb 6 2020, 4:48 PM

Herald added subscribers: Petar.Avramovic, hiraditya, t-tye and 7 others. · View Herald Transcript

ping

LGTM

This revision is now accepted and ready to land.Feb 12 2020, 3:03 PM

e174c278ca2f91bd2cae4fc849ba888fa7f851a9

Revision Contents

Path

Size

llvm/

lib/

Target/

AMDGPU/

AMDGPURegisterBankInfo.cpp

47 lines

test/

CodeGen/

AMDGPU/

GlobalISel/

divergent-control-flow.ll

142 lines

regbankselect-amdgcn.div.fmas.mir

23 lines

regbankselect-and-s1.mir

19 lines

regbankselect-icmp.mir

127 lines

regbankselect-icmp.s16.mir

10 lines

regbankselect-or.mir

20 lines

regbankselect-phi-s1.mir

140 lines

regbankselect-phi.mir

196 lines

regbankselect-xor.mir

27 lines

Diff 243053

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 565 Lines • ▼ Show 20 Lines	case TargetOpcode::G_SEXTLOAD: {
// the mubuf instructions support this kind of load, but probably for only		// the mubuf instructions support this kind of load, but probably for only
// gfx7 and older. However, the addressing mode matching in the instruction		// gfx7 and older. However, the addressing mode matching in the instruction
// selector should be able to do a better job of detecting and selecting		// selector should be able to do a better job of detecting and selecting
// these kinds of loads from the vgpr = load vgpr mapping.		// these kinds of loads from the vgpr = load vgpr mapping.

return AltMappings;		return AltMappings;

}		}
case TargetOpcode::G_ICMP: {
// TODO: Should report 32-bit for scalar output type.
unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands
AltMappings.push_back(&SSMapping);

const InstructionMapping &VVMapping = getInstructionMapping(4, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1),
nullptr, // Predicate operand.
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size)}),
4); // Num Operands
AltMappings.push_back(&VVMapping);

return AltMappings;
}
case TargetOpcode::G_SELECT: {		case TargetOpcode::G_SELECT: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);		unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
const InstructionMapping &SSMapping = getInstructionMapping(1, 1,		const InstructionMapping &SSMapping = getInstructionMapping(1, 1,
getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),		AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
4); // Num Operands		4); // Num Operands
▲ Show 20 Lines • Show All 999 Lines • ▼ Show 20 Lines	if (HasCarryIn) {
Register NewSrcReg = MRI.createGenericVirtualRegister(S32);		Register NewSrcReg = MRI.createGenericVirtualRegister(S32);
MRI.setRegBank(NewSrcReg, AMDGPU::SGPRRegBank);		MRI.setRegBank(NewSrcReg, AMDGPU::SGPRRegBank);
B.buildZExt(NewSrcReg, MI.getOperand(4).getReg());		B.buildZExt(NewSrcReg, MI.getOperand(4).getReg());
MI.getOperand(4).setReg(NewSrcReg);		MI.getOperand(4).setReg(NewSrcReg);
}		}

MachineBasicBlock *MBB = MI.getParent();		MachineBasicBlock *MBB = MI.getParent();
B.setInsertPt(*MBB, std::next(MI.getIterator()));		B.setInsertPt(*MBB, std::next(MI.getIterator()));
B.buildTrunc(DstReg, NewDstReg);
		// If we had a constrained VCC result register, a copy was inserted to VCC
		// from SGPR.
		SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0));
		if (DefRegs.empty())
		DefRegs.push_back(DstReg);
		B.buildTrunc(DefRegs[0], NewDstReg);
return;		return;
}		}
case AMDGPU::G_SELECT: {		case AMDGPU::G_SELECT: {
Register DstReg = MI.getOperand(0).getReg();		Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);		LLT DstTy = MRI.getType(DstReg);

SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1));		SmallVector<Register, 1> CondRegs(OpdMapper.getVRegs(1));
if (CondRegs.empty())		if (CondRegs.empty())
▲ Show 20 Lines • Show All 1,416 Lines • ▼ Show 20 Lines	const ValueMapping *ValMapping =
AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);		AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
OpdsMapping[0] = ValMapping;		OpdsMapping[0] = ValMapping;
OpdsMapping[1] = getValueMappingForPtr(MRI, MI.getOperand(1).getReg());		OpdsMapping[1] = getValueMappingForPtr(MRI, MI.getOperand(1).getReg());
break;		break;
}		}
case AMDGPU::G_ICMP: {		case AMDGPU::G_ICMP: {
auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());		auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();		unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();

		// See if the result register has already been constrained to vcc, which may
		// happen due to control flow intrinsic lowering.
		unsigned DstBank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,
		AMDGPU::SGPRRegBankID);
unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);		unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);		unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);

bool CanUseSCC = Op2Bank == AMDGPU::SGPRRegBankID &&		bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID &&
		Op2Bank == AMDGPU::SGPRRegBankID &&
Op3Bank == AMDGPU::SGPRRegBankID &&		Op3Bank == AMDGPU::SGPRRegBankID &&
(Size == 32 \|\| (Size == 64 &&		(Size == 32 \|\| (Size == 64 &&
(Pred == CmpInst::ICMP_EQ \|\| Pred == CmpInst::ICMP_NE) &&		(Pred == CmpInst::ICMP_EQ \|\| Pred == CmpInst::ICMP_NE) &&
Subtarget.hasScalarCompareEq64()));		Subtarget.hasScalarCompareEq64()));

unsigned Op0Bank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;		DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID;
		unsigned SrcBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;

// TODO: Use 32-bit for scalar output size.		// TODO: Use 32-bit for scalar output size.
// SCC results will need to be copied to a 32-bit SGPR virtual register.		// SCC results will need to be copied to a 32-bit SGPR virtual register.
const unsigned ResultSize = 1;		const unsigned ResultSize = 1;

OpdsMapping[0] = AMDGPU::getValueMapping(Op0Bank, ResultSize);		OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize);
OpdsMapping[1] = nullptr; // Predicate Operand.		OpdsMapping[2] = AMDGPU::getValueMapping(SrcBank, Size);
OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);		OpdsMapping[3] = AMDGPU::getValueMapping(SrcBank, Size);
OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
break;		break;
}		}
case AMDGPU::G_EXTRACT_VECTOR_ELT: {		case AMDGPU::G_EXTRACT_VECTOR_ELT: {
// VGPR index can be used for waterfall when indexing a SGPR vector.		// VGPR index can be used for waterfall when indexing a SGPR vector.
unsigned SrcBankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);		unsigned SrcBankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();		unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();		unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
unsigned IdxSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();		unsigned IdxSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
▲ Show 20 Lines • Show All 610 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

	Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
	endif:			endif:
	%v = phi i32 [ %val, %if.true ], [ undef, %entry ]			%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
	ret i32 %v			ret i32 %v

	if.true:			if.true:
	%val = load volatile i32, i32 addrspace(1)* undef			%val = load volatile i32, i32 addrspace(1)* undef
	br label %endif			br label %endif
	}			}

				; Make sure and 1 is inserted on llvm.amdgcn.if
				define i32 @divergent_if_nonboolean_condition0(i32 %value) {
				; CHECK-LABEL: divergent_if_nonboolean_condition0:
				; CHECK: ; %bb.0: ; %entry
				; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
				; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
				; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
				; CHECK-NEXT: ; implicit-def: $vgpr0
				; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
				; CHECK-NEXT: s_cbranch_execz BB2_2
				; CHECK-NEXT: ; %bb.1: ; %if.true
				; CHECK-NEXT: global_load_dword v0, v[0:1], off
				; CHECK-NEXT: BB2_2: ; %endif
				; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
				; CHECK-NEXT: s_waitcnt vmcnt(0)
				; CHECK-NEXT: s_setpc_b64 s[30:31]
				entry:
				%c = trunc i32 %value to i1
				br i1 %c, label %if.true, label %endif

				if.true:
				%val = load volatile i32, i32 addrspace(1)* undef
				br label %endif

				endif:
				%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
				ret i32 %v
				}

				; Make sure and 1 is inserted on llvm.amdgcn.if
				define i32 @divergent_if_nonboolean_condition1(i32 addrspace(1)* %ptr) {
				; CHECK-LABEL: divergent_if_nonboolean_condition1:
				; CHECK: ; %bb.0: ; %entry
				; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
				; CHECK-NEXT: global_load_dword v0, v[0:1], off
				; CHECK-NEXT: s_waitcnt vmcnt(0)
				; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
				; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
				; CHECK-NEXT: ; implicit-def: $vgpr0
				; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
				; CHECK-NEXT: s_cbranch_execz BB3_2
				; CHECK-NEXT: ; %bb.1: ; %if.true
				; CHECK-NEXT: global_load_dword v0, v[0:1], off
				; CHECK-NEXT: BB3_2: ; %endif
				; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
				; CHECK-NEXT: s_waitcnt vmcnt(0)
				; CHECK-NEXT: s_setpc_b64 s[30:31]
				entry:
				%value = load i32, i32 addrspace(1)* %ptr
				%c = trunc i32 %value to i1
				br i1 %c, label %if.true, label %endif

				if.true:
				%val = load volatile i32, i32 addrspace(1)* undef
				br label %endif

				endif:
				%v = phi i32 [ %val, %if.true ], [ undef, %entry ]
				ret i32 %v
				}

				@external_constant = external addrspace(4) constant i32, align 4
				@const.ptr = external addrspace(4) constant float*, align 4

				; Make sure this case compiles. G_ICMP was mis-mapped due to having
				; the result register class constrained by llvm.amdgcn.if lowering.
				define void @constrained_if_register_class() {
				; CHECK-LABEL: constrained_if_register_class:
				; CHECK: ; %bb.0: ; %bb
				; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
				; CHECK-NEXT: s_getpc_b64 s[4:5]
				; CHECK-NEXT: s_add_u32 s4, s4, external_constant@gotpcrel32@lo+4
				; CHECK-NEXT: s_addc_u32 s5, s5, external_constant@gotpcrel32@hi+4
				; CHECK-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
				; CHECK-NEXT: s_waitcnt lgkmcnt(0)
				; CHECK-NEXT: s_load_dword s6, s[4:5], 0x0
				; CHECK-NEXT: s_getpc_b64 s[4:5]
				; CHECK-NEXT: s_add_u32 s4, s4, const.ptr@gotpcrel32@lo+4
				; CHECK-NEXT: s_addc_u32 s5, s5, const.ptr@gotpcrel32@hi+4
				; CHECK-NEXT: s_waitcnt lgkmcnt(0)
				; CHECK-NEXT: s_cmp_lg_u32 s6, 0
				; CHECK-NEXT: s_cselect_b32 s6, 1, 0
				; CHECK-NEXT: s_and_b32 s6, s6, 1
				; CHECK-NEXT: s_cmp_lg_u32 s6, 0
				; CHECK-NEXT: s_cbranch_scc1 BB4_6
				; CHECK-NEXT: ; %bb.1: ; %bb2
				; CHECK-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
				; CHECK-NEXT: s_mov_b32 s4, -1
				; CHECK-NEXT: s_waitcnt lgkmcnt(0)
				; CHECK-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
				; CHECK-NEXT: s_waitcnt lgkmcnt(0)
				; CHECK-NEXT: v_mov_b32_e32 v0, s6
				; CHECK-NEXT: v_mov_b32_e32 v1, s7
				; CHECK-NEXT: flat_load_dword v0, v[0:1]
				; CHECK-NEXT: v_cmp_ne_u32_e64 s[6:7], 0, 1
				; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
				; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, 1.0, v0
				; CHECK-NEXT: s_xor_b64 s[8:9], vcc, s[6:7]
				; CHECK-NEXT: s_and_saveexec_b64 s[6:7], s[8:9]
				; CHECK-NEXT: ; %bb.2: ; %bb7
				; CHECK-NEXT: s_mov_b32 s4, 0
				; CHECK-NEXT: ; %bb.3: ; %bb8
				; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
				; CHECK-NEXT: v_cmp_eq_u32_e64 s[6:7], s4, 0
				; CHECK-NEXT: s_and_saveexec_b64 s[4:5], s[6:7]
				; CHECK-NEXT: s_cbranch_execz BB4_5
				; CHECK-NEXT: ; %bb.4: ; %bb11
				; CHECK-NEXT: v_mov_b32_e32 v0, 4.0
				; CHECK-NEXT: buffer_store_dword v0, v0, s[0:3], s33 offen
				; CHECK-NEXT: BB4_5: ; %Flow
				; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
				; CHECK-NEXT: BB4_6: ; %bb12
				; CHECK-NEXT: s_waitcnt vmcnt(0)
				; CHECK-NEXT: s_setpc_b64 s[30:31]
				bb:
				%tmp = load i32, i32 addrspace(4)* @external_constant
				%ptr = load float, float addrspace(4)* @const.ptr
				%tmp1 = icmp ne i32 %tmp, 0
				br i1 %tmp1, label %bb12, label %bb2

				bb2:
				%tmp4 = load float, float* %ptr, align 4
				%tmp5 = fcmp olt float %tmp4, 1.0
				%tmp6 = or i1 %tmp5, false
				br i1 %tmp6, label %bb8, label %bb7

				bb7:
				br label %bb8

				bb8:
				%tmp9 = phi i32 [ 0, %bb7 ], [ -1, %bb2 ]
				%tmp10 = icmp eq i32 %tmp9, 0
				br i1 %tmp10, label %bb11, label %bb12

				bb11:
				store float 4.0, float addrspace(5)* undef, align 4
				br label %bb12

				bb12:
				ret void
				}

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir

Show All 38 Lines	body: \|
bb.0:		bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0		liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
; CHECK-LABEL: name: div_fmas_sss_vcc		; CHECK-LABEL: name: div_fmas_sss_vcc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2		; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]		; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[ICMP]](s1)		; CHECK: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
		; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[ICMP]](s1)
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
%2:_(s32) = COPY $sgpr2		%2:_(s32) = COPY $sgpr2
%3:_(s32) = COPY $vgpr0		%3:_(s32) = COPY $vgpr0
%4:_(s32) = G_CONSTANT i32 0		%4:_(s32) = G_CONSTANT i32 0
%5:_(s1) = G_ICMP intpred(eq), %3, %4		%5:_(s1) = G_ICMP intpred(eq), %3, %4
%6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5		%6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5
...		...

---		---
name: div_fmas_vss_vcc		name: div_fmas_vss_vcc
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr1		liveins: $vgpr0, $vgpr1, $sgpr0, $sgpr1
; CHECK-LABEL: name: div_fmas_vss_vcc		; CHECK-LABEL: name: div_fmas_vss_vcc
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]		; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]]
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)		; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY4]](s32), [[COPY5]](s32), [[ICMP]](s1)		; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
		; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY5]](s32), [[COPY6]](s32), [[ICMP]](s1)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
%3:_(s32) = COPY $vgpr1		%3:_(s32) = COPY $vgpr1
%4:_(s32) = G_CONSTANT i32 0		%4:_(s32) = G_CONSTANT i32 0
%5:_(s1) = G_ICMP intpred(eq), %3, %4		%5:_(s1) = G_ICMP intpred(eq), %3, %4
%6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5		%6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5
...		...

---		---
name: div_fmas_vvv_vcc		name: div_fmas_vvv_vcc
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3		liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
; CHECK-LABEL: name: div_fmas_vvv_vcc		; CHECK-LABEL: name: div_fmas_vvv_vcc
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2		; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3		; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[C]]		; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY3]](s32), [[COPY4]]
; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[ICMP]](s1)		; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[ICMP]](s1)
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $vgpr2		%2:_(s32) = COPY $vgpr2
%3:_(s32) = COPY $vgpr3		%3:_(s32) = COPY $vgpr3
%4:_(s32) = G_CONSTANT i32 0		%4:_(s32) = G_CONSTANT i32 0
%5:_(s1) = G_ICMP intpred(eq), %3, %4		%5:_(s1) = G_ICMP intpred(eq), %3, %4
%6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5		%6:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.div.fmas), %0, %1, %2, %5
...		...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir

Show First 20 Lines • Show All 80 Lines • ▼ Show 20 Lines

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: and_s1_vcc_vcc		; CHECK-LABEL: name: and_s1_vcc_vcc
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
		; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]		; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_CONSTANT i32 0		%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2		%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2		%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4		%5:_(s1) = G_AND %3, %4
...		...
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines	body: \|
bb.0:		bb.0:
liveins: $sgpr0, $vgpr0		liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: and_s1_scc_vcc		; CHECK-LABEL: name: and_s1_scc_vcc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]		; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
		; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY3]], [[ICMP1]]
%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0		%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_CONSTANT i32 0		%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2		%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2		%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4		%5:_(s1) = G_AND %3, %4
...		...

---		---
name: and_s1_vcc_scc		name: and_s1_vcc_scc
legalized: true		legalized: true

body: \|		body: \|
bb.0:		bb.0:
liveins: $vgpr0, $vgpr1		liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: and_s1_vcc_scc		; CHECK-LABEL: name: and_s1_vcc_scc
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY2]]
		; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]		; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_CONSTANT i32 0		%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2		%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2		%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4		%5:_(s1) = G_AND %3, %4
...		...
▲ Show 20 Lines • Show All 106 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir

	Show All 30 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX7-LABEL: name: icmp_eq_s32_sv			; GFX7-LABEL: name: icmp_eq_s32_sv
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY1]]
	; GFX8-LABEL: name: icmp_eq_s32_sv			; GFX8-LABEL: name: icmp_eq_s32_sv
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_ICMP intpred(eq), %0, %1			%2:_(s1) = G_ICMP intpred(eq), %0, %1
	...			...

	---			---
	name: icmp_eq_s32_vs			name: icmp_eq_s32_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX7-LABEL: name: icmp_eq_s32_vs			; GFX7-LABEL: name: icmp_eq_s32_vs
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]
	; GFX8-LABEL: name: icmp_eq_s32_vs			; GFX8-LABEL: name: icmp_eq_s32_vs
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY2]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_ICMP intpred(eq), %1, %0			%2:_(s1) = G_ICMP intpred(eq), %1, %0
	...			...

	---			---
	name: icmp_eq_s32_vv			name: icmp_eq_s32_vv
	legalized: true			legalized: true
	Show All 19 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $sgpr2_sgpr3			liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
	; GFX7-LABEL: name: icmp_eq_s64_ss			; GFX7-LABEL: name: icmp_eq_s64_ss
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3			; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY3]]
	; GFX8-LABEL: name: icmp_eq_s64_ss			; GFX8-LABEL: name: icmp_eq_s64_ss
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3			; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
	; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]			; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
	; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)			; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $sgpr2_sgpr3			%1:_(s64) = COPY $sgpr2_sgpr3
	%2:_(s1) = G_ICMP intpred(eq), %0, %1			%2:_(s1) = G_ICMP intpred(eq), %0, %1
	...			...

	---			---
	name: icmp_eq_s64_sv			name: icmp_eq_s64_sv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0_vgpr1			liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
	; GFX7-LABEL: name: icmp_eq_s64_sv			; GFX7-LABEL: name: icmp_eq_s64_sv
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY1]]
	; GFX8-LABEL: name: icmp_eq_s64_sv			; GFX8-LABEL: name: icmp_eq_s64_sv
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s64), [[COPY1]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $vgpr0_vgpr1			%1:_(s64) = COPY $vgpr0_vgpr1
	%2:_(s1) = G_ICMP intpred(eq), %0, %1			%2:_(s1) = G_ICMP intpred(eq), %0, %1
	...			...

	---			---
	name: icmp_eq_s64_vs			name: icmp_eq_s64_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0_vgpr1			liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
	; GFX7-LABEL: name: icmp_eq_s64_vs			; GFX7-LABEL: name: icmp_eq_s64_vs
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY2]]
	; GFX8-LABEL: name: icmp_eq_s64_vs			; GFX8-LABEL: name: icmp_eq_s64_vs
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s64), [[COPY2]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $vgpr0_vgpr1			%1:_(s64) = COPY $vgpr0_vgpr1
	%2:_(s1) = G_ICMP intpred(eq), %1, %0			%2:_(s1) = G_ICMP intpred(eq), %1, %0
	...			...

	---			---
	name: icmp_eq_s64_vv			name: icmp_eq_s64_vv
	legalized: true			legalized: true
	Show All 19 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $sgpr2_sgpr3			liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
	; GFX7-LABEL: name: icmp_ne_s64_ss			; GFX7-LABEL: name: icmp_ne_s64_ss
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3			; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s64), [[COPY3]]
	; GFX8-LABEL: name: icmp_ne_s64_ss			; GFX8-LABEL: name: icmp_ne_s64_ss
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3			; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
	; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]			; GFX8: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]
	; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)			; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $sgpr2_sgpr3			%1:_(s64) = COPY $sgpr2_sgpr3
	%2:_(s1) = G_ICMP intpred(ne), %0, %1			%2:_(s1) = G_ICMP intpred(ne), %0, %1
	...			...

	---			---
	name: icmp_ne_s64_sv			name: icmp_ne_s64_sv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0_vgpr1			liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
	; GFX7-LABEL: name: icmp_ne_s64_sv			; GFX7-LABEL: name: icmp_ne_s64_sv
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s64), [[COPY1]]
	; GFX8-LABEL: name: icmp_ne_s64_sv			; GFX8-LABEL: name: icmp_ne_s64_sv
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s64), [[COPY1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s64), [[COPY1]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $vgpr0_vgpr1			%1:_(s64) = COPY $vgpr0_vgpr1
	%2:_(s1) = G_ICMP intpred(ne), %0, %1			%2:_(s1) = G_ICMP intpred(ne), %0, %1
	...			...

	---			---
	name: icmp_ne_s64_vs			name: icmp_ne_s64_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0_vgpr1			liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
	; GFX7-LABEL: name: icmp_ne_s64_vs			; GFX7-LABEL: name: icmp_ne_s64_vs
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
	; GFX8-LABEL: name: icmp_ne_s64_vs			; GFX8-LABEL: name: icmp_ne_s64_vs
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s64), [[COPY2]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $vgpr0_vgpr1			%1:_(s64) = COPY $vgpr0_vgpr1
	%2:_(s1) = G_ICMP intpred(ne), %1, %0			%2:_(s1) = G_ICMP intpred(ne), %1, %0
	...			...

	---			---
	name: icmp_ne_s64_vv			name: icmp_ne_s64_vv
	legalized: true			legalized: true
	Show All 19 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $sgpr2_sgpr3			liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
	; GFX7-LABEL: name: icmp_slt_s64_ss			; GFX7-LABEL: name: icmp_slt_s64_ss
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3			; GFX7: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY3]]
	; GFX8-LABEL: name: icmp_slt_s64_ss			; GFX8-LABEL: name: icmp_slt_s64_ss
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3			; GFX8: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY3]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $sgpr2_sgpr3			%1:_(s64) = COPY $sgpr2_sgpr3
	%2:_(s1) = G_ICMP intpred(slt), %0, %1			%2:_(s1) = G_ICMP intpred(slt), %0, %1
	...			...

	---			---
	name: icmp_slt_s64_sv			name: icmp_slt_s64_sv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0_vgpr1			liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
	; GFX7-LABEL: name: icmp_slt_s64_sv			; GFX7-LABEL: name: icmp_slt_s64_sv
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY1]]
	; GFX8-LABEL: name: icmp_slt_s64_sv			; GFX8-LABEL: name: icmp_slt_s64_sv
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY2]](s64), [[COPY1]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $vgpr0_vgpr1			%1:_(s64) = COPY $vgpr0_vgpr1
	%2:_(s1) = G_ICMP intpred(slt), %0, %1			%2:_(s1) = G_ICMP intpred(slt), %0, %1
	...			...

	---			---
	name: icmp_slt_s64_vs			name: icmp_slt_s64_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0_sgpr1, $vgpr0_vgpr1			liveins: $sgpr0_sgpr1, $vgpr0_vgpr1
	; GFX7-LABEL: name: icmp_slt_s64_vs			; GFX7-LABEL: name: icmp_slt_s64_vs
	; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX7: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY]]			; GFX7: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY2]]
	; GFX8-LABEL: name: icmp_slt_s64_vs			; GFX8-LABEL: name: icmp_slt_s64_vs
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1			; GFX8: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY1]](s64), [[COPY2]]
	%0:_(s64) = COPY $sgpr0_sgpr1			%0:_(s64) = COPY $sgpr0_sgpr1
	%1:_(s64) = COPY $vgpr0_vgpr1			%1:_(s64) = COPY $vgpr0_vgpr1
	%2:_(s1) = G_ICMP intpred(slt), %1, %0			%2:_(s1) = G_ICMP intpred(slt), %1, %0
	...			...

	---			---
	name: icmp_slt_s64_vv			name: icmp_slt_s64_vv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0_vgpr1, $vgpr2_vgpr3			liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
	; GFX7-LABEL: name: icmp_slt_s64_vv			; GFX7-LABEL: name: icmp_slt_s64_vv
	; GFX7: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX7: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3			; GFX7: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
	; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]			; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
	; GFX8-LABEL: name: icmp_slt_s64_vv			; GFX8-LABEL: name: icmp_slt_s64_vv
	; GFX8: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1			; GFX8: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]			; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(slt), [[COPY]](s64), [[COPY1]]
	%0:_(s64) = COPY $vgpr0_vgpr1			%0:_(s64) = COPY $vgpr0_vgpr1
	%1:_(s64) = COPY $vgpr2_vgpr3			%1:_(s64) = COPY $vgpr2_vgpr3
	%2:_(s1) = G_ICMP intpred(slt), %0, %1			%2:_(s1) = G_ICMP intpred(slt), %0, %1
	...			...

				# Result is already constrained to be VCC bank, despite scalar inputs.
				---
				name: map_icmp_already_vcc_bank_sgpr_inputs
				legalized: true
				tracksRegLiveness: true
				body: \|
				bb.0:
				liveins: $sgpr0, $sgpr1

				; GFX7-LABEL: name: map_icmp_already_vcc_bank_sgpr_inputs
				; GFX7: liveins: $sgpr0, $sgpr1
				; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
				; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
				; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX7: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
				; GFX7: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
				; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1)
				; GFX8-LABEL: name: map_icmp_already_vcc_bank_sgpr_inputs
				; GFX8: liveins: $sgpr0, $sgpr1
				; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
				; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
				; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX8: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
				; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1)
				%0:_(s32) = COPY $sgpr0
				%1:_(s32) = COPY $sgpr1
				%2:vcc(s1) = G_ICMP intpred(eq), %0, %1
				S_ENDPGM 0, implicit %2
				...

				# Result is already con strained to be VCC bank, despite scalar inputs
				# and also has a register class.
				---
				name: map_icmp_already_vcc_regclass_sgpr_inputs
				legalized: true
				tracksRegLiveness: true
				body: \|
				bb.0:
				liveins: $sgpr0, $sgpr1

				; GFX7-LABEL: name: map_icmp_already_vcc_regclass_sgpr_inputs
				; GFX7: liveins: $sgpr0, $sgpr1
				; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
				; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
				; GFX7: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX7: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
				; GFX7: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
				; GFX7: S_ENDPGM 0, implicit [[ICMP]](s1)
				; GFX8-LABEL: name: map_icmp_already_vcc_regclass_sgpr_inputs
				; GFX8: liveins: $sgpr0, $sgpr1
				; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
				; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
				; GFX8: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
				; GFX8: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
				; GFX8: [[ICMP:%[0-9]+]]:sreg_64_xexec(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
				; GFX8: S_ENDPGM 0, implicit [[ICMP]](s1)
				%0:_(s32) = COPY $sgpr0
				%1:_(s32) = COPY $sgpr1
				%2:sreg_64_xexec(s1) = G_ICMP intpred(eq), %0, %1
				S_ENDPGM 0, implicit %2
				...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir

	# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py			# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX8 %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX8 %s
	# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX8 %s			# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s \| FileCheck -check-prefix=GFX8 %s

	---			---
	name: icmp_eq_s16_ss			name: icmp_eq_s16_ss
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $sgpr1			liveins: $sgpr0, $sgpr1
	; GFX8-LABEL: name: icmp_eq_s16_ss			; GFX8-LABEL: name: icmp_eq_s16_ss
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1			; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
	; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)			; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
	; GFX8: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)			; GFX8: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
				; GFX8: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s16), [[COPY3]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $sgpr1			%1:_(s32) = COPY $sgpr1
	%2:_(s16) = G_TRUNC %0			%2:_(s16) = G_TRUNC %0
	%3:_(s16) = G_TRUNC %1			%3:_(s16) = G_TRUNC %1
	%4:_(s1) = G_ICMP intpred(eq), %2, %3			%4:_(s1) = G_ICMP intpred(eq), %2, %3
	...			...

	---			---
	name: icmp_eq_s16_sv			name: icmp_eq_s16_sv
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: icmp_eq_s16_sv			; GFX8-LABEL: name: icmp_eq_s16_sv
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)			; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
	; GFX8: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)			; GFX8: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s16), [[TRUNC1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s16) = G_TRUNC %0			%2:_(s16) = G_TRUNC %0
	%3:_(s16) = G_TRUNC %1			%3:_(s16) = G_TRUNC %1
	%4:_(s1) = G_ICMP intpred(eq), %2, %3			%4:_(s1) = G_ICMP intpred(eq), %2, %3
	...			...

	---			---
	name: icmp_eq_s16_vs			name: icmp_eq_s16_vs
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; GFX8-LABEL: name: icmp_eq_s16_vs			; GFX8-LABEL: name: icmp_eq_s16_vs
	; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)			; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
	; GFX8: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)			; GFX8: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
	; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]			; GFX8: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
				; GFX8: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s16), [[TRUNC1]]
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s16) = G_TRUNC %0			%2:_(s16) = G_TRUNC %0
	%3:_(s16) = G_TRUNC %1			%3:_(s16) = G_TRUNC %1
	%4:_(s1) = G_ICMP intpred(eq), %2, %3			%4:_(s1) = G_ICMP intpred(eq), %2, %3
	...			...

	---			---
	Show All 18 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir

	Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: or_i1_vcc_vcc			; CHECK-LABEL: name: or_i1_vcc_vcc
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
	; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
	; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY2]]
				; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
				; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY3]]
	; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[ICMP]], [[ICMP1]]			; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[ICMP]], [[ICMP1]]
	; CHECK: S_NOP 0, implicit [[OR]](s1)			; CHECK: S_NOP 0, implicit [[OR]](s1)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32) = G_CONSTANT i32 0			%2:_(s32) = G_CONSTANT i32 0
	%4:_(s1) = G_ICMP intpred(ne), %0, %2			%4:_(s1) = G_ICMP intpred(ne), %0, %2
	%5:_(s1) = G_ICMP intpred(ne), %1, %2			%5:_(s1) = G_ICMP intpred(ne), %1, %2
	%6:_(s1) = G_OR %4, %5			%6:_(s1) = G_OR %4, %5
	S_NOP 0, implicit %6			S_NOP 0, implicit %6
	...			...

	---			---
	name: or_i1_scc_vcc			name: or_i1_scc_vcc
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: or_i1_scc_vcc			; CHECK-LABEL: name: or_i1_scc_vcc
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
	; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)			; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
	; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)			; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
	; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP1]]			; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
				; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY3]], [[ICMP1]]
	; CHECK: S_NOP 0, implicit [[OR]](s1)			; CHECK: S_NOP 0, implicit [[OR]](s1)
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32) = G_CONSTANT i32 0			%2:_(s32) = G_CONSTANT i32 0
	%4:_(s1) = G_ICMP intpred(ne), %0, %2			%4:_(s1) = G_ICMP intpred(ne), %0, %2
	%5:_(s1) = G_ICMP intpred(ne), %1, %2			%5:_(s1) = G_ICMP intpred(ne), %1, %2
	%6:_(s1) = G_OR %4, %5			%6:_(s1) = G_OR %4, %5
	S_NOP 0, implicit %6			S_NOP 0, implicit %6
	▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true
	body: \|			body: \|
	bb.0.entry:			bb.0.entry:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: or_i1_s_trunc_vcc			; CHECK-LABEL: name: or_i1_s_trunc_vcc
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)			; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
	; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY1]]
	; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[ICMP]]			; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
				; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY3]], [[ICMP]]
	; CHECK: S_NOP 0, implicit [[OR]](s1)			; CHECK: S_NOP 0, implicit [[OR]](s1)
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_TRUNC %0			%2:_(s1) = G_TRUNC %0
	%3:_(s1) = G_ICMP intpred(ne), %0, %1			%3:_(s1) = G_ICMP intpred(ne), %0, %1
	%4:_(s1) = G_OR %2, %3			%4:_(s1) = G_OR %2, %3
	S_NOP 0, implicit %4			S_NOP 0, implicit %4
	...			...
	▲ Show 20 Lines • Show All 528 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Lines	body: \|
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0		; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0

%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0		%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_scc_sbranch		; FAST-LABEL: name: phi_s1_vcc_scc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $sgpr0, $sgpr1		; FAST: liveins: $vgpr0, $sgpr0, $sgpr1
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_vcc_sbranch		; FAST-LABEL: name: phi_s1_vcc_vcc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $vgpr1, $sgpr0		; FAST: liveins: $vgpr0, $vgpr1, $sgpr0
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0		; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_s_sbranch		; FAST-LABEL: name: phi_s1_vcc_s_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $sgpr0, $sgpr1		; FAST: liveins: $vgpr0, $sgpr0, $sgpr1
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 34 Lines	body: \|
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1

%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0		%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_v_sbranch		; FAST-LABEL: name: phi_s1_vcc_v_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $vgpr1, $sgpr0		; FAST: liveins: $vgpr0, $vgpr1, $sgpr0
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)		; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1
; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0		; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)		; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1
; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
Show All 34 Lines	body: \|
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)		; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1
; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0		; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)		; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1
; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
▲ Show 20 Lines • Show All 454 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir

Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines	body: \|
; FAST-LABEL: name: phi_s32_ss_vcc_sbranch		; FAST-LABEL: name: phi_s32_ss_vcc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $sgpr0, $sgpr1, $vgpr0		; FAST: liveins: $sgpr0, $sgpr1, $vgpr0
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; FAST: G_BRCOND [[ICMP]](s1), %bb.1		; FAST: G_BRCOND [[ICMP]](s1), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST: $sgpr0 = COPY [[PHI]](s32)		; FAST: $sgpr0 = COPY [[PHI]](s32)
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
; GREEDY-LABEL: name: phi_s32_ss_vcc_sbranch		; GREEDY-LABEL: name: phi_s32_ss_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0		; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1		; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; GREEDY: $sgpr0 = COPY [[PHI]](s32)		; GREEDY: $sgpr0 = COPY [[PHI]](s32)
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0

%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1		%1:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s32_sv_vcc_sbranch		; FAST-LABEL: name: phi_s32_sv_vcc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $sgpr0, $vgpr0, $vgpr1		; FAST: liveins: $sgpr0, $vgpr0, $vgpr1
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; FAST: G_BRCOND [[ICMP]](s1), %bb.1		; FAST: G_BRCOND [[ICMP]](s1), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST: $vgpr0 = COPY [[PHI]](s32)		; FAST: $vgpr0 = COPY [[PHI]](s32)
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
; GREEDY-LABEL: name: phi_s32_sv_vcc_sbranch		; GREEDY-LABEL: name: phi_s32_sv_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $sgpr0, $vgpr0, $vgpr1		; GREEDY: liveins: $sgpr0, $vgpr0, $vgpr1
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1		; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; GREEDY: $vgpr0 = COPY [[PHI]](s32)		; GREEDY: $vgpr0 = COPY [[PHI]](s32)
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $sgpr0, $vgpr0, $vgpr1		liveins: $sgpr0, $vgpr0, $vgpr1

%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0		%1:_(s32) = COPY $vgpr0
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s32_vs_vcc_sbranch		; FAST-LABEL: name: phi_s32_vs_vcc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $sgpr0, $vgpr1		; FAST: liveins: $vgpr0, $sgpr0, $vgpr1
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; FAST: G_BRCOND [[ICMP]](s1), %bb.1		; FAST: G_BRCOND [[ICMP]](s1), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST: $vgpr0 = COPY [[PHI]](s32)		; FAST: $vgpr0 = COPY [[PHI]](s32)
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
; GREEDY-LABEL: name: phi_s32_vs_vcc_sbranch		; GREEDY-LABEL: name: phi_s32_vs_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $vgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $vgpr1
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1		; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; GREEDY: $vgpr0 = COPY [[PHI]](s32)		; GREEDY: $vgpr0 = COPY [[PHI]](s32)
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $vgpr1		liveins: $vgpr0, $sgpr0, $vgpr1

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s32_vv_vcc_sbranch		; FAST-LABEL: name: phi_s32_vv_vcc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $vgpr1, $vgpr2		; FAST: liveins: $vgpr0, $vgpr1, $vgpr2
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2		; FAST: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; FAST: G_BRCOND [[ICMP]](s1), %bb.1		; FAST: G_BRCOND [[ICMP]](s1), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; FAST: $vgpr0 = COPY [[PHI]](s32)		; FAST: $vgpr0 = COPY [[PHI]](s32)
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31
; GREEDY-LABEL: name: phi_s32_vv_vcc_sbranch		; GREEDY-LABEL: name: phi_s32_vv_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $vgpr2		; GREEDY: liveins: $vgpr0, $vgpr1, $vgpr2
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2		; GREEDY: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1		; GREEDY: G_BRCOND [[ICMP]](s1), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY4]](s32), %bb.1
; GREEDY: $vgpr0 = COPY [[PHI]](s32)		; GREEDY: $vgpr0 = COPY [[PHI]](s32)
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $vgpr2		liveins: $vgpr0, $vgpr1, $vgpr2

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
▲ Show 20 Lines • Show All 251 Lines • ▼ Show 20 Lines	body: \|
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_scc_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0		; GREEDY: liveins: $sgpr0, $sgpr1, $vgpr0
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $sgpr0, $sgpr1, $vgpr0		liveins: $sgpr0, $sgpr1, $vgpr0

%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0		%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_scc_sbranch		; FAST-LABEL: name: phi_s1_vcc_scc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $sgpr0, $sgpr1		; FAST: liveins: $vgpr0, $sgpr0, $sgpr1
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_scc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP2]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)		; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_vcc_sbranch		; FAST-LABEL: name: phi_s1_vcc_vcc_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $vgpr1, $sgpr0		; FAST: liveins: $vgpr0, $vgpr1, $sgpr0
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0		; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
▲ Show 20 Lines • Show All 375 Lines • ▼ Show 20 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_s_sbranch		; FAST-LABEL: name: phi_s1_vcc_s_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $sgpr0, $sgpr1		; FAST: liveins: $vgpr0, $sgpr0, $sgpr1
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_s_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY3]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[COPY4]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0		%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 34 Lines	body: \|
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1		; FAST: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; FAST: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_s_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1		; GREEDY: liveins: $vgpr0, $sgpr0, $sgpr1
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)		; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY4]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[COPY3]](s1), %bb.0, [[ICMP1]](s1), %bb.1
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)		; GREEDY: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY4]], [[COPY5]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY5]], [[COPY6]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $sgpr0, $sgpr1		liveins: $vgpr0, $sgpr0, $sgpr1

%0:_(s32) = COPY $sgpr0		%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0		%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr1		%2:_(s32) = COPY $sgpr1
Show All 25 Lines	body: \|
; FAST-LABEL: name: phi_s1_vcc_v_sbranch		; FAST-LABEL: name: phi_s1_vcc_v_sbranch
; FAST: bb.0:		; FAST: bb.0:
; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; FAST: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; FAST: liveins: $vgpr0, $vgpr1, $sgpr0		; FAST: liveins: $vgpr0, $vgpr1, $sgpr0
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; FAST: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)		; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1
; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch		; GREEDY-LABEL: name: phi_s1_vcc_v_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0		; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]
; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP1]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[C2]]
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)		; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC1]](s1)
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[SELECT]](s32), %bb.0, [[ANYEXT]](s32), %bb.1
; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
Show All 34 Lines	body: \|
; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)		; FAST: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; FAST: G_BRCOND [[ZEXT]](s32), %bb.1		; FAST: G_BRCOND [[ZEXT]](s32), %bb.1
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.1:		; FAST: bb.1:
; FAST: successors: %bb.2(0x80000000)		; FAST: successors: %bb.2(0x80000000)
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; FAST: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; FAST: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; FAST: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]		; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]
; FAST: G_BR %bb.2		; FAST: G_BR %bb.2
; FAST: bb.2:		; FAST: bb.2:
; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1		; FAST: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1
; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; FAST: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; FAST: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; FAST: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; FAST: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; FAST: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch		; GREEDY-LABEL: name: phi_s1_v_vcc_sbranch
; GREEDY: bb.0:		; GREEDY: bb.0:
; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)		; GREEDY: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0		; GREEDY: liveins: $vgpr0, $vgpr1, $sgpr0
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0		; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1		; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0		; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)		; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]		; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)		; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)		; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC1]](s1)
; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)		; GREEDY: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[TRUNC]](s1)
; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1		; GREEDY: G_BRCOND [[ZEXT]](s32), %bb.1
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.1:		; GREEDY: bb.1:
; GREEDY: successors: %bb.2(0x80000000)		; GREEDY: successors: %bb.2(0x80000000)
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]		; GREEDY: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
		; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[COPY3]]
; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1		; GREEDY: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0		; GREEDY: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]		; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[C2]]
; GREEDY: G_BR %bb.2		; GREEDY: G_BR %bb.2
; GREEDY: bb.2:		; GREEDY: bb.2:
; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1		; GREEDY: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[ANYEXT]](s32), %bb.0, [[SELECT]](s32), %bb.1
; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)		; GREEDY: [[TRUNC2:%[0-9]+]]:vgpr(s1) = G_TRUNC [[PHI]](s32)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)		; GREEDY: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[TRUNC2]](s1)
; GREEDY: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)		; GREEDY: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]		; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY]]
; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)		; GREEDY: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT1]](s32)
bb.0:		bb.0:
successors: %bb.1, %bb.2		successors: %bb.1, %bb.2
liveins: $vgpr0, $vgpr1, $sgpr0		liveins: $vgpr0, $vgpr1, $sgpr0

%0:_(s32) = COPY $vgpr0		%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1		%1:_(s32) = COPY $vgpr1
%2:_(s32) = COPY $sgpr0		%2:_(s32) = COPY $sgpr0
▲ Show 20 Lines • Show All 646 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir

	Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: xor_i1_vcc_vcc			; CHECK-LABEL: name: xor_i1_vcc_vcc
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
	; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
	; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY2]]
				; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
				; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY3]]
	; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[ICMP1]]			; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[ICMP1]]
	; CHECK: S_NOP 0, implicit [[XOR]](s1)			; CHECK: S_NOP 0, implicit [[XOR]](s1)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = COPY $vgpr1			%1:_(s32) = COPY $vgpr1
	%2:_(s32) = G_CONSTANT i32 0			%2:_(s32) = G_CONSTANT i32 0
	%4:_(s1) = G_ICMP intpred(ne), %0, %2			%4:_(s1) = G_ICMP intpred(ne), %0, %2
	%5:_(s1) = G_ICMP intpred(ne), %1, %2			%5:_(s1) = G_ICMP intpred(ne), %1, %2
	%6:_(s1) = G_XOR %4, %5			%6:_(s1) = G_XOR %4, %5
	S_NOP 0, implicit %6			S_NOP 0, implicit %6
	...			...

	---			---
	name: xor_i1_scc_vcc			name: xor_i1_scc_vcc
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: xor_i1_scc_vcc			; CHECK-LABEL: name: xor_i1_scc_vcc
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
	; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
	; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)			; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32)
	; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)			; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[COPY2]]
	; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP1]]			; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
				; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY3]], [[ICMP1]]
	; CHECK: S_NOP 0, implicit [[XOR]](s1)			; CHECK: S_NOP 0, implicit [[XOR]](s1)
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s32) = G_CONSTANT i32 0			%2:_(s32) = G_CONSTANT i32 0
	%4:_(s1) = G_ICMP intpred(ne), %0, %2			%4:_(s1) = G_ICMP intpred(ne), %0, %2
	%5:_(s1) = G_ICMP intpred(ne), %1, %2			%5:_(s1) = G_ICMP intpred(ne), %1, %2
	%6:_(s1) = G_XOR %4, %5			%6:_(s1) = G_XOR %4, %5
	S_NOP 0, implicit %6			S_NOP 0, implicit %6
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	legalized: true			legalized: true
	body: \|			body: \|
	bb.0.entry:			bb.0.entry:
	liveins: $sgpr0, $vgpr0			liveins: $sgpr0, $vgpr0
	; CHECK-LABEL: name: xor_i1_s_trunc_vcc			; CHECK-LABEL: name: xor_i1_s_trunc_vcc
	; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0			; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
	; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)			; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
	; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]			; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
	; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)			; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY2]](s32), [[COPY1]]
	; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[ICMP]]			; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
				; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY3]], [[ICMP]]
	; CHECK: S_NOP 0, implicit [[XOR]](s1)			; CHECK: S_NOP 0, implicit [[XOR]](s1)
	%0:_(s32) = COPY $sgpr0			%0:_(s32) = COPY $sgpr0
	%1:_(s32) = COPY $vgpr0			%1:_(s32) = COPY $vgpr0
	%2:_(s1) = G_TRUNC %0			%2:_(s1) = G_TRUNC %0
	%3:_(s1) = G_ICMP intpred(ne), %0, %1			%3:_(s1) = G_ICMP intpred(ne), %0, %1
	%4:_(s1) = G_XOR %2, %3			%4:_(s1) = G_XOR %2, %3
	S_NOP 0, implicit %4			S_NOP 0, implicit %4
	...			...
	▲ Show 20 Lines • Show All 531 Lines • ▼ Show 20 Lines
	legalized: true			legalized: true

	body: \|			body: \|
	bb.0:			bb.0:
	liveins: $vgpr0, $vgpr1			liveins: $vgpr0, $vgpr1
	; CHECK-LABEL: name: xor_i1_vcc_constant			; CHECK-LABEL: name: xor_i1_vcc_constant
	; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0			; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
	; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0			; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
	; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]			; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
				; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
	; CHECK: [[C1:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true			; CHECK: [[C1:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true
	; CHECK: [[COPY1:%[0-9]+]]:vcc(s1) = COPY [[C1]](s1)			; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[C1]](s1)
	; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[COPY1]]			; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[ICMP]], [[COPY2]]
	; CHECK: S_NOP 0, implicit [[XOR]](s1)			; CHECK: S_NOP 0, implicit [[XOR]](s1)
	%0:_(s32) = COPY $vgpr0			%0:_(s32) = COPY $vgpr0
	%1:_(s32) = G_CONSTANT i32 0			%1:_(s32) = G_CONSTANT i32 0
	%2:_(s1) = G_ICMP intpred(ne), %0, %1			%2:_(s1) = G_ICMP intpred(ne), %0, %1
	%3:_(s1) = G_CONSTANT i1 true			%3:_(s1) = G_CONSTANT i1 true
	%4:_(s1) = G_XOR %2, %3			%4:_(s1) = G_XOR %2, %3
	S_NOP 0, implicit %4			S_NOP 0, implicit %4
	...			...