[NFC][RISCV] Fixing typo in comment.

[lenary]

"We expand those pseudo-instructions while". (There are other pseudo-instructions that are expanded much earlier).

[ncv]

[NFC][RISCV] Fixing typo in comment.

Additionally reformatting to keep under 80 columns.

[ncv]

In D73984#1858926, @lenary wrote:

"We expand those pseudo-instructions while". (There are other pseudo-instructions that are expanded much earlier).

Done, also reformatted and minor grammar nits adressed.

[lenary]

LGTM. Do you need me to commit this for you?

[ncv]

In D73984#1860274, @lenary wrote:

LGTM. Do you need me to commit this for you?

Nope, I'll go ahead and land it now. Thanks!

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

 
 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new RISCVMCCodeEmitter(Ctx, MCII);
 }
 
 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
-// relocation types. We those pseudo-instructions while encoding them, meaning
-// AUIPC and JALR won't go through RISCV MC to MC compressed instruction
-// transformation. This is acceptable because AUIPC has no 16-bit form and
-// C_JALR have no immediate operand field.  We let linker relaxation deal with
-// it. When linker relaxation enabled, AUIPC and JALR have chance relax to JAL.
-// If C extension is enabled, JAL has chance relax to C_JAL.
+// relocation types. We expand those pseudo-instructions while encoding them,
+// meaning AUIPC and JALR won't go through RISCV MC to MC compressed
+// instruction transformation. This is acceptable because AUIPC has no 16-bit
+// form and C_JALR has no immediate operand field.  We let linker relaxation
+// deal with it. When linker relaxation is enabled, AUIPC and JALR have a
+// chance to relax to JAL.
+// If the C extension is enabled, JAL has a chance relax to C_JAL.
 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
                                             SmallVectorImpl<MCFixup> &Fixups,
                                             const MCSubtargetInfo &STI) const {
   MCInst TmpInst;
   MCOperand Func;
   Register Ra;
   if (MI.getOpcode() == RISCV::PseudoTAIL) {
     Func = MI.getOperand(0);